| Line 62... |
Line 62... |
port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active
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rstn_i : in std_ulogic; -- global reset line, low-active
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-- host access --
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-- host access --
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src_i : in std_ulogic; -- access type (0: data, 1:instruction)
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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cancel_i : in std_ulogic; -- cancel current bus transaction
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cancel_i : in std_ulogic; -- cancel current bus transaction
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic; -- transfer error
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err_o : out std_ulogic; -- transfer error
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priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
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-- wishbone interface --
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-- wishbone interface --
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wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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wb_we_o : out std_ulogic; -- read/write
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wb_we_o : out std_ulogic; -- read/write
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wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
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wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
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rdat : std_ulogic_vector(31 downto 0);
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rdat : std_ulogic_vector(31 downto 0);
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sel : std_ulogic_vector(3 downto 0);
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sel : std_ulogic_vector(3 downto 0);
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ack : std_ulogic;
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ack : std_ulogic;
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err : std_ulogic;
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err : std_ulogic;
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timeout : std_ulogic_vector(index_size_f(wb_timeout_c)-1 downto 0);
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timeout : std_ulogic_vector(index_size_f(wb_timeout_c)-1 downto 0);
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src : std_ulogic;
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priv : std_ulogic_vector(1 downto 0);
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end record;
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end record;
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signal ctrl : ctrl_t;
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signal ctrl : ctrl_t;
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signal stb_int : std_ulogic;
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signal stb_int, cyc_int : std_ulogic;
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signal cyc_int : std_ulogic;
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begin
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 155... |
Line 160... |
ctrl.rdat <= (others => '0');
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ctrl.rdat <= (others => '0');
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ctrl.sel <= (others => '0');
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ctrl.sel <= (others => '0');
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ctrl.timeout <= (others => '0');
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ctrl.timeout <= (others => '0');
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ctrl.ack <= '0';
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ctrl.ack <= '0';
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ctrl.err <= '0';
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ctrl.err <= '0';
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ctrl.src <= '0';
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ctrl.priv <= "00";
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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-- defaults --
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-- defaults --
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ctrl.state_prev <= ctrl.state;
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ctrl.state_prev <= ctrl.state;
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ctrl.rdat <= (others => '0');
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ctrl.rdat <= (others => '0');
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ctrl.ack <= '0';
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ctrl.ack <= '0';
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| Line 175... |
Line 182... |
-- buffer all outgoing signals --
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-- buffer all outgoing signals --
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ctrl.we <= wren_i;
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ctrl.we <= wren_i;
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ctrl.adr <= addr_i;
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ctrl.adr <= addr_i;
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ctrl.wdat <= data_i;
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ctrl.wdat <= data_i;
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ctrl.sel <= ben_i;
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ctrl.sel <= ben_i;
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ctrl.src <= src_i;
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ctrl.priv <= priv_i;
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-- valid read/write access --
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-- valid read/write access --
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if ((wb_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then
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if ((wb_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then
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ctrl.state <= BUSY;
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ctrl.state <= BUSY;
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end process bus_arbiter;
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end process bus_arbiter;
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-- host access --
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-- host access --
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data_o <= ctrl.rdat;
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data_o <= ctrl.rdat;
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ack_o <= ctrl.ack;
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ack_o <= ctrl.ack;
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err_o <= ctrl.err;
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err_o <= ctrl.err;
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-- wishbone interface --
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-- wishbone interface --
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wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode
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wb_tag_o(1) <= '0'; -- 0=secure, 1=non-secure
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wb_tag_o(2) <= ctrl.src; -- 0=data access, 1=instruction access
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wb_adr_o <= ctrl.adr;
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wb_adr_o <= ctrl.adr;
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wb_dat_o <= ctrl.wdat;
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wb_dat_o <= ctrl.wdat;
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wb_we_o <= ctrl.we;
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wb_we_o <= ctrl.we;
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wb_sel_o <= ctrl.sel;
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wb_sel_o <= ctrl.sel;
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wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int;
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wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int;
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