| Line 99... |
Line 99... |
signal int_dmem_acc, int_dmem_acc_real : std_ulogic;
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signal int_dmem_acc, int_dmem_acc_real : std_ulogic;
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signal int_boot_acc : std_ulogic;
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signal int_boot_acc : std_ulogic;
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signal wb_access : std_ulogic;
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signal wb_access : std_ulogic;
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-- bus arbiter
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-- bus arbiter
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type ctrl_state_t is (IDLE, BUSY, CANCELED);
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type ctrl_state_t is (IDLE, BUSY, CANCELED, RESYNC);
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type ctrl_t is record
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type ctrl_t is record
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state : ctrl_state_t;
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state : ctrl_state_t;
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state_prev : ctrl_state_t;
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state_prev : ctrl_state_t;
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we : std_ulogic;
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we : std_ulogic;
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rd_req : std_ulogic;
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rd_req : std_ulogic;
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| Line 202... |
Line 202... |
elsif (wb_ack_i = '1') then -- normal bus termination
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elsif (wb_ack_i = '1') then -- normal bus termination
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ctrl.ack <= '1';
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ctrl.ack <= '1';
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ctrl.state <= IDLE;
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ctrl.state <= IDLE;
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end if;
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end if;
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when CANCELED => --
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when CANCELED => -- wait for cycle to be completed either by peripheral or by timeout (ignore result of transfer)
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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ctrl.wr_req <= ctrl.wr_req or wren_i; -- buffer new request
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ctrl.wr_req <= ctrl.wr_req or wren_i; -- buffer new request
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ctrl.rd_req <= ctrl.rd_req or rden_i; -- buffer new request
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ctrl.rd_req <= ctrl.rd_req or rden_i; -- buffer new request
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-- wait for bus.peripheral to ACK transfer (as "aborted" but still somehow "completed")
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-- wait for bus.peripheral to ACK transfer (as "aborted" but still somehow "completed")
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-- or wait for a timeout and force termination
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-- or wait for a timeout and force termination
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ctrl.timeout <= std_ulogic_vector(unsigned(ctrl.timeout) - 1); -- timeout counter
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ctrl.timeout <= std_ulogic_vector(unsigned(ctrl.timeout) - 1); -- timeout counter
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if (wb_ack_i = '1') or (or_all_f(ctrl.timeout) = '0') then
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if (wb_ack_i = '1') or (or_all_f(ctrl.timeout) = '0') then
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ctrl.state <= RESYNC;
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end if;
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when RESYNC => -- make sure transfer is done!
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-- ------------------------------------------------------------
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if (wb_ack_i = '0') then
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ctrl.state <= IDLE;
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ctrl.state <= IDLE;
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end if;
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end if;
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when others => -- undefined
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when others => -- undefined
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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| Line 239... |
Line 245... |
wb_sel_o <= ctrl.sel;
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wb_sel_o <= ctrl.sel;
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wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int;
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wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int;
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wb_cyc_o <= cyc_int;
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wb_cyc_o <= cyc_int;
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stb_int <= '1' when ((ctrl.state = BUSY) and (ctrl.state_prev = IDLE)) else '0';
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stb_int <= '1' when ((ctrl.state = BUSY) and (ctrl.state_prev = IDLE)) else '0';
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cyc_int <= '0' when (ctrl.state = IDLE) else '1';
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cyc_int <= '0' when ((ctrl.state = IDLE) or (ctrl.state = RESYNC)) else '1';
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end neorv32_wishbone_rtl;
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end neorv32_wishbone_rtl;
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No newline at end of file
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No newline at end of file
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