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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
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-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The interface provides registers for all outgoing signals. If the host cancels a running #
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-- # The interface provides registers for all outgoing and for all incoming signals. If the host #
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-- # transfer, the Wishbone arbiter still waits some time for the bus system to ACK the transfer #
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-- # cancels an activetransfer, the Wishbone arbiter still waits some time for the bus system to #
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-- # before the arbiter forces termination. #
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-- # ACK/ERR the transfer before the arbiter forces termination. #
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-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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-- # #
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-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address #
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-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address #
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-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). #
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-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). #
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-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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-- # #
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-- # All bus accesses from the CPU, which do not target the internal IO region / the internal #
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-- # All bus accesses from the CPU, which do not target the internal IO region / the internal #
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-- # bootlloader / the internal instruction or data memories (if implemented), are delegated via #
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-- # bootlloader / the internal instruction or data memories (if implemented), are delegated via #
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-- # this Wishbone gateway to the external bus interface. Accessed peripherals can have a response #
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-- # this Wishbone gateway to the external bus interface. Accessed peripherals can have a response #
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-- # latency of up to neorv32_package.vhd:bus_timeout_c - 2 cycles. #
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-- # latency of up to BUS_TIMEOUT - 2 cycles. #
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-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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-- # #
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-- # This interface supports classic/standard Wishbone transactions (WB_PIPELINED_MODE = false) #
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-- # This interface supports classic/standard Wishbone transactions (WB_PIPELINED_MODE = false) #
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-- # and also pipelined transactions (WB_PIPELINED_MODE = true). #
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-- # and also pipelined transactions (WB_PIPELINED_MODE = true). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- Internal instruction memory --
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-- Internal instruction memory --
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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-- Internal data memory --
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-- Internal data memory --
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MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 4*1024 -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
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-- Bus Timeout --
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BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active
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rstn_i : in std_ulogic; -- global reset line, low-active
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end neorv32_wishbone;
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end neorv32_wishbone;
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architecture neorv32_wishbone_rtl of neorv32_wishbone is
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architecture neorv32_wishbone_rtl of neorv32_wishbone is
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-- constants --
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-- constants --
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constant xbus_timeout_c : natural := bus_timeout_c/4;
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constant xbus_timeout_c : natural := BUS_TIMEOUT/4;
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-- access control --
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-- access control --
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signal int_imem_acc : std_ulogic;
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signal int_imem_acc : std_ulogic;
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signal int_dmem_acc : std_ulogic;
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signal int_dmem_acc : std_ulogic;
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signal int_boot_acc : std_ulogic;
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signal int_boot_acc : std_ulogic;
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begin
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- max bus timeout latency lower than recommended --
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-- max bus timeout latency lower than recommended --
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assert not (bus_timeout_c <= 32) report "NEORV32 PROCESSOR CONFIG ERROR: Bus timeout (neorv32_package.vhd:bus_timeout_c) should be >32 when using external bus interface." severity error;
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assert not (BUS_TIMEOUT <= 32) report "NEORV32 PROCESSOR CONFIG WARNING: Bus timeout should be >32 when using external bus interface." severity warning;
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-- external memory iterface protocol + max timeout latency notifier (warning) --
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-- external memory iterface protocol + max timeout latency notifier (warning) --
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assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol with max latency = " & integer'image(bus_timeout_c) & " cycles." severity note;
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assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol." severity note;
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assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG WARNING! Implementing external memory interface using PIEPLINED Wishbone protocol with max latency = " & integer'image(bus_timeout_c) & " cycles." severity warning;
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assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG NOTE! Implementing external memory interface using PIEPLINED Wishbone protocol." severity note;
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-- endianness --
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-- endianness --
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assert not (xbus_big_endian_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Using LITTLE-ENDIAN byte order for external memory interface." severity note;
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assert not (xbus_big_endian_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Using LITTLE-ENDIAN byte order for external memory interface." severity note;
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assert not (xbus_big_endian_c = true) report "NEORV32 PROCESSOR CONFIG NOTE: Using BIG-ENDIAN byte order for external memory interface." severity note;
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assert not (xbus_big_endian_c = true) report "NEORV32 PROCESSOR CONFIG NOTE: Using BIG-ENDIAN byte order for external memory interface." severity note;
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