| Line 77... |
Line 77... |
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
cancel_i : in std_ulogic; -- cancel current bus transaction
|
cancel_i : in std_ulogic; -- cancel current bus transaction
|
lock_i : in std_ulogic; -- locked/exclusive bus access
|
excl_i : in std_ulogic; -- exclusive access request
|
|
excl_o : out std_ulogic; -- state of exclusiv access (set if failed)
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
err_o : out std_ulogic; -- transfer error
|
err_o : out std_ulogic; -- transfer error
|
priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
|
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag
|
wb_tag_o : out std_ulogic_vector(03 downto 0); -- request tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_lock_o : out std_ulogic; -- locked/exclusive bus access
|
wb_tag_i : in std_ulogic; -- response tag
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_err_i : in std_ulogic -- transfer error
|
wb_err_i : in std_ulogic -- transfer error
|
);
|
);
|
end neorv32_wishbone;
|
end neorv32_wishbone;
|
|
|
| Line 122... |
Line 123... |
sel : std_ulogic_vector(3 downto 0);
|
sel : std_ulogic_vector(3 downto 0);
|
ack : std_ulogic;
|
ack : std_ulogic;
|
err : std_ulogic;
|
err : std_ulogic;
|
timeout : std_ulogic_vector(index_size_f(xbus_timeout_c)-1 downto 0);
|
timeout : std_ulogic_vector(index_size_f(xbus_timeout_c)-1 downto 0);
|
src : std_ulogic;
|
src : std_ulogic;
|
lock : std_ulogic;
|
excl : std_ulogic;
|
|
exclr : std_ulogic; -- response
|
priv : std_ulogic_vector(1 downto 0);
|
priv : std_ulogic_vector(1 downto 0);
|
end record;
|
end record;
|
signal ctrl : ctrl_t;
|
signal ctrl : ctrl_t;
|
signal stb_int : std_ulogic;
|
signal stb_int : std_ulogic;
|
signal cyc_int : std_ulogic;
|
signal cyc_int : std_ulogic;
|
| Line 170... |
Line 172... |
ctrl.sel <= (others => '0');
|
ctrl.sel <= (others => '0');
|
ctrl.timeout <= (others => '0');
|
ctrl.timeout <= (others => '0');
|
ctrl.ack <= '0';
|
ctrl.ack <= '0';
|
ctrl.err <= '0';
|
ctrl.err <= '0';
|
ctrl.src <= '0';
|
ctrl.src <= '0';
|
ctrl.lock <= '0';
|
ctrl.excl <= '0';
|
|
ctrl.exclr <= '0';
|
ctrl.priv <= "00";
|
ctrl.priv <= "00";
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- defaults --
|
-- defaults --
|
ctrl.rdat <= (others => '0');
|
ctrl.rdat <= (others => '0');
|
ctrl.ack <= '0';
|
ctrl.ack <= '0';
|
ctrl.err <= '0';
|
ctrl.err <= '0';
|
|
ctrl.exclr <= '0';
|
ctrl.timeout <= std_ulogic_vector(to_unsigned(xbus_timeout_c, index_size_f(xbus_timeout_c)));
|
ctrl.timeout <= std_ulogic_vector(to_unsigned(xbus_timeout_c, index_size_f(xbus_timeout_c)));
|
|
|
-- state machine --
|
-- state machine --
|
case ctrl.state is
|
case ctrl.state is
|
|
|
| Line 197... |
Line 201... |
else
|
else
|
ctrl.wdat <= bswap32_f(data_i);
|
ctrl.wdat <= bswap32_f(data_i);
|
ctrl.sel <= bit_rev_f(ben_i);
|
ctrl.sel <= bit_rev_f(ben_i);
|
end if;
|
end if;
|
ctrl.src <= src_i;
|
ctrl.src <= src_i;
|
ctrl.lock <= lock_i;
|
ctrl.excl <= excl_i;
|
ctrl.priv <= priv_i;
|
ctrl.priv <= priv_i;
|
-- valid new or buffered read/write request --
|
-- valid new or buffered read/write request --
|
if ((xbus_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then
|
if ((xbus_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then
|
ctrl.state <= BUSY;
|
ctrl.state <= BUSY;
|
end if;
|
end if;
|
|
|
when BUSY => -- transfer in progress
|
when BUSY => -- transfer in progress
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl.rdat <= wb_dat_i;
|
ctrl.rdat <= wb_dat_i;
|
|
ctrl.exclr <= wb_tag_i; -- set if exclusive access success
|
if (cancel_i = '1') then -- transfer canceled by host
|
if (cancel_i = '1') then -- transfer canceled by host
|
ctrl.state <= CANCELED;
|
ctrl.state <= CANCELED;
|
elsif (wb_err_i = '1') then -- abnormal bus termination
|
elsif (wb_err_i = '1') then -- abnormal bus termination
|
ctrl.err <= '1';
|
ctrl.err <= '1';
|
ctrl.state <= CANCELED;
|
ctrl.state <= CANCELED;
|
| Line 246... |
Line 251... |
|
|
-- host access --
|
-- host access --
|
data_o <= ctrl.rdat when (xbus_big_endian_c = true) else bswap32_f(ctrl.rdat); -- endianness conversion
|
data_o <= ctrl.rdat when (xbus_big_endian_c = true) else bswap32_f(ctrl.rdat); -- endianness conversion
|
ack_o <= ctrl.ack;
|
ack_o <= ctrl.ack;
|
err_o <= ctrl.err;
|
err_o <= ctrl.err;
|
|
excl_o <= ctrl.exclr;
|
|
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode
|
wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode
|
wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure
|
wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure
|
wb_tag_o(2) <= ctrl.src; -- 0 = data access, 1 = instruction access
|
wb_tag_o(2) <= ctrl.src; -- 0 = data access, 1 = instruction access
|
|
wb_tag_o(3) <= ctrl.excl; -- 1 = exclusive access request
|
|
|
wb_adr_o <= ctrl.adr;
|
wb_adr_o <= ctrl.adr;
|
wb_dat_o <= ctrl.wdat;
|
wb_dat_o <= ctrl.wdat;
|
wb_we_o <= ctrl.we;
|
wb_we_o <= ctrl.we;
|
wb_sel_o <= ctrl.sel;
|
wb_sel_o <= ctrl.sel;
|
wb_lock_o <= ctrl.lock;
|
|
wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int;
|
wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int;
|
wb_cyc_o <= cyc_int;
|
wb_cyc_o <= cyc_int;
|
|
|
stb_int <= '1' when (ctrl.state = BUSY) else '0';
|
stb_int <= '1' when (ctrl.state = BUSY) else '0';
|
cyc_int <= '0' when (ctrl.state = IDLE) or (ctrl.state = RESYNC) else '1';
|
cyc_int <= '0' when (ctrl.state = IDLE) or (ctrl.state = RESYNC) else '1';
|
