| Line 7... |
Line 7... |
-- # #
|
-- # #
|
-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address #
|
-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address #
|
-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). #
|
-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). #
|
-- # #
|
-- # #
|
-- # All bus accesses from the CPU, which do not target the internal IO region / the internal #
|
-- # All bus accesses from the CPU, which do not target the internal IO region / the internal #
|
-- # bootlloader / the internal instruction or data memories (if implemented), are delegated via #
|
-- # bootloader / the internal instruction or data memories (if implemented), are delegated via #
|
-- # this Wishbone gateway to the external bus interface. Accessed peripherals can have a response #
|
-- # this Wishbone gateway to the external bus interface. Accessed peripherals can have a response #
|
-- # latency of up to BUS_TIMEOUT - 2 cycles. #
|
-- # latency of up to BUS_TIMEOUT - 2 cycles. #
|
-- # #
|
-- # #
|
-- # This interface supports classic/standard Wishbone transactions (WB_PIPELINED_MODE = false) #
|
-- # This interface supports classic/standard Wishbone transactions (WB_PIPELINED_MODE = false) #
|
-- # and also pipelined transactions (WB_PIPELINED_MODE = true). #
|
-- # and also pipelined transactions (WB_PIPELINED_MODE = true). #
|
| Line 76... |
Line 76... |
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
cancel_i : in std_ulogic; -- cancel current bus transaction
|
lock_i : in std_ulogic; -- exclusive access request
|
excl_i : in std_ulogic; -- exclusive access request
|
|
excl_o : out std_ulogic; -- state of exclusiv access (set if failed)
|
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
err_o : out std_ulogic; -- transfer error
|
err_o : out std_ulogic; -- transfer error
|
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
|
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_tag_o : out std_ulogic_vector(03 downto 0); -- request tag
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_tag_i : in std_ulogic; -- response tag
|
wb_lock_o : out std_ulogic; -- exclusive access request
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_err_i : in std_ulogic -- transfer error
|
wb_err_i : in std_ulogic -- transfer error
|
);
|
);
|
end neorv32_wishbone;
|
end neorv32_wishbone;
|
|
|
architecture neorv32_wishbone_rtl of neorv32_wishbone is
|
architecture neorv32_wishbone_rtl of neorv32_wishbone is
|
|
|
-- constants --
|
-- timeout enable --
|
constant xbus_timeout_c : natural := BUS_TIMEOUT/4;
|
constant timeout_en_c : boolean := boolean(BUS_TIMEOUT /= 0); -- timeout enabled if BUS_TIMEOUT > 0
|
|
|
-- access control --
|
-- access control --
|
signal int_imem_acc : std_ulogic;
|
signal int_imem_acc : std_ulogic;
|
signal int_dmem_acc : std_ulogic;
|
signal int_dmem_acc : std_ulogic;
|
signal int_boot_acc : std_ulogic;
|
signal int_boot_acc : std_ulogic;
|
signal xbus_access : std_ulogic;
|
signal xbus_access : std_ulogic;
|
|
|
-- bus arbiter
|
-- bus arbiter
|
type ctrl_state_t is (IDLE, BUSY, CANCELED, RESYNC);
|
type ctrl_state_t is (IDLE, BUSY, RESYNC);
|
type ctrl_t is record
|
type ctrl_t is record
|
state : ctrl_state_t;
|
state : ctrl_state_t;
|
we : std_ulogic;
|
we : std_ulogic;
|
rd_req : std_ulogic;
|
rd_req : std_ulogic;
|
wr_req : std_ulogic;
|
wr_req : std_ulogic;
|
| Line 121... |
Line 119... |
wdat : std_ulogic_vector(31 downto 0);
|
wdat : std_ulogic_vector(31 downto 0);
|
rdat : std_ulogic_vector(31 downto 0);
|
rdat : std_ulogic_vector(31 downto 0);
|
sel : std_ulogic_vector(3 downto 0);
|
sel : std_ulogic_vector(3 downto 0);
|
ack : std_ulogic;
|
ack : std_ulogic;
|
err : std_ulogic;
|
err : std_ulogic;
|
timeout : std_ulogic_vector(index_size_f(xbus_timeout_c)-1 downto 0);
|
timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
|
src : std_ulogic;
|
src : std_ulogic;
|
excl : std_ulogic;
|
lock : std_ulogic;
|
exclr : std_ulogic; -- response
|
|
priv : std_ulogic_vector(1 downto 0);
|
priv : std_ulogic_vector(1 downto 0);
|
end record;
|
end record;
|
signal ctrl : ctrl_t;
|
signal ctrl : ctrl_t;
|
signal stb_int : std_ulogic;
|
signal stb_int : std_ulogic;
|
signal cyc_int : std_ulogic;
|
signal cyc_int : std_ulogic;
|
|
|
begin
|
begin
|
|
|
-- Sanity Checks --------------------------------------------------------------------------
|
-- Sanity Checks --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- max bus timeout latency lower than recommended --
|
-- bus timeout --
|
assert not (BUS_TIMEOUT <= 32) report "NEORV32 PROCESSOR CONFIG WARNING: Bus timeout should be >32 when using external bus interface." severity warning;
|
assert not (BUS_TIMEOUT /= 0) report "NEORV32 PROCESSOR CONFIG WARNING: Using auto-timeout for external bus interface (" & integer'image(BUS_TIMEOUT) & " cycles)." severity warning;
|
-- external memory iterface protocol + max timeout latency notifier (warning) --
|
assert not (BUS_TIMEOUT /= 0) report "NEORV32 PROCESSOR CONFIG WARNING: Using no auto-timeout for external bus interface (might cause permanent CPU stall)." severity warning;
|
|
-- external memory interface protocol + max timeout latency notifier (warning) --
|
assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol." severity note;
|
assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol." severity note;
|
assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG NOTE! Implementing external memory interface using PIEPLINED Wishbone protocol." severity note;
|
assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG NOTE! Implementing external memory interface using PIEPLINED Wishbone protocol." severity note;
|
-- endianness --
|
-- endianness --
|
assert not (xbus_big_endian_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Using LITTLE-ENDIAN byte order for external memory interface." severity note;
|
assert not (xbus_big_endian_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Using LITTLE-ENDIAN byte order for external memory interface." severity note;
|
assert not (xbus_big_endian_c = true) report "NEORV32 PROCESSOR CONFIG NOTE: Using BIG-ENDIAN byte order for external memory interface." severity note;
|
assert not (xbus_big_endian_c = true) report "NEORV32 PROCESSOR CONFIG NOTE: Using BIG-ENDIAN byte order for external memory interface." severity note;
|
| Line 161... |
Line 159... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
bus_arbiter: process(rstn_i, clk_i)
|
bus_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
ctrl.state <= IDLE;
|
ctrl.state <= IDLE;
|
ctrl.we <= '0';
|
ctrl.we <= def_rst_val_c;
|
ctrl.rd_req <= '0';
|
ctrl.rd_req <= '0';
|
ctrl.wr_req <= '0';
|
ctrl.wr_req <= '0';
|
ctrl.adr <= (others => '0');
|
ctrl.adr <= (others => def_rst_val_c);
|
ctrl.wdat <= (others => '0');
|
ctrl.wdat <= (others => def_rst_val_c);
|
ctrl.rdat <= (others => '0');
|
ctrl.rdat <= (others => def_rst_val_c);
|
ctrl.sel <= (others => '0');
|
ctrl.sel <= (others => def_rst_val_c);
|
ctrl.timeout <= (others => '0');
|
ctrl.timeout <= (others => def_rst_val_c);
|
ctrl.ack <= '0';
|
ctrl.ack <= def_rst_val_c;
|
ctrl.err <= '0';
|
ctrl.err <= def_rst_val_c;
|
ctrl.src <= '0';
|
ctrl.src <= def_rst_val_c;
|
ctrl.excl <= '0';
|
ctrl.lock <= def_rst_val_c;
|
ctrl.exclr <= '0';
|
ctrl.priv <= (others => def_rst_val_c);
|
ctrl.priv <= "00";
|
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- defaults --
|
-- defaults --
|
ctrl.rdat <= (others => '0');
|
ctrl.rdat <= (others => '0');
|
ctrl.ack <= '0';
|
ctrl.ack <= '0';
|
ctrl.err <= '0';
|
ctrl.err <= '0';
|
ctrl.exclr <= '0';
|
ctrl.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
|
ctrl.timeout <= std_ulogic_vector(to_unsigned(xbus_timeout_c, index_size_f(xbus_timeout_c)));
|
|
|
|
-- state machine --
|
-- state machine --
|
case ctrl.state is
|
case ctrl.state is
|
|
|
when IDLE => -- waiting for host request
|
when IDLE => -- waiting for host request
|
| Line 201... |
Line 197... |
else
|
else
|
ctrl.wdat <= bswap32_f(data_i);
|
ctrl.wdat <= bswap32_f(data_i);
|
ctrl.sel <= bit_rev_f(ben_i);
|
ctrl.sel <= bit_rev_f(ben_i);
|
end if;
|
end if;
|
ctrl.src <= src_i;
|
ctrl.src <= src_i;
|
ctrl.excl <= excl_i;
|
ctrl.lock <= lock_i;
|
ctrl.priv <= priv_i;
|
ctrl.priv <= priv_i;
|
-- valid new or buffered read/write request --
|
-- valid new or buffered read/write request --
|
if ((xbus_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req) and (not cancel_i)) = '1') then
|
if ((xbus_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then
|
ctrl.state <= BUSY;
|
ctrl.state <= BUSY;
|
end if;
|
end if;
|
|
|
when BUSY => -- transfer in progress
|
when BUSY => -- transfer in progress
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl.rdat <= wb_dat_i;
|
ctrl.rdat <= wb_dat_i;
|
ctrl.exclr <= wb_tag_i; -- set if exclusive access success
|
if (wb_err_i = '1') then -- abnormal bus termination
|
if (cancel_i = '1') then -- transfer canceled by host
|
|
ctrl.state <= CANCELED;
|
|
elsif (wb_err_i = '1') then -- abnormal bus termination
|
|
ctrl.err <= '1';
|
ctrl.err <= '1';
|
ctrl.state <= CANCELED;
|
ctrl.state <= IDLE;
|
elsif (wb_ack_i = '1') then -- normal bus termination
|
elsif (wb_ack_i = '1') then -- normal bus termination
|
ctrl.ack <= '1';
|
ctrl.ack <= '1';
|
ctrl.state <= IDLE;
|
ctrl.state <= IDLE;
|
|
elsif (timeout_en_c = true) and (or_all_f(ctrl.timeout) = '0') then -- valid timeout
|
|
ctrl.err <= '1';
|
|
ctrl.state <= IDLE;
|
end if;
|
end if;
|
|
-- timeout counter --
|
when CANCELED => -- wait for cycle to be completed either by peripheral or by timeout (ignore result of transfer)
|
if (timeout_en_c = true) then
|
-- ------------------------------------------------------------
|
|
ctrl.wr_req <= ctrl.wr_req or wren_i; -- buffer new request
|
|
ctrl.rd_req <= ctrl.rd_req or rden_i; -- buffer new request
|
|
-- wait for bus.peripheral to ACK transfer (as "aborted" but still somehow "completed")
|
|
-- or wait for a timeout and force termination
|
|
ctrl.timeout <= std_ulogic_vector(unsigned(ctrl.timeout) - 1); -- timeout counter
|
ctrl.timeout <= std_ulogic_vector(unsigned(ctrl.timeout) - 1); -- timeout counter
|
if (wb_ack_i = '1') or (or_all_f(ctrl.timeout) = '0') then
|
|
ctrl.state <= RESYNC;
|
|
end if;
|
end if;
|
|
|
when RESYNC => -- make sure transfer is done!
|
when RESYNC => -- make sure transfer is done!
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl.wr_req <= ctrl.wr_req or wren_i; -- buffer new request
|
ctrl.wr_req <= ctrl.wr_req or wren_i; -- buffer new request
|
| Line 253... |
Line 242... |
|
|
-- host access --
|
-- host access --
|
data_o <= ctrl.rdat when (xbus_big_endian_c = true) else bswap32_f(ctrl.rdat); -- endianness conversion
|
data_o <= ctrl.rdat when (xbus_big_endian_c = true) else bswap32_f(ctrl.rdat); -- endianness conversion
|
ack_o <= ctrl.ack;
|
ack_o <= ctrl.ack;
|
err_o <= ctrl.err;
|
err_o <= ctrl.err;
|
excl_o <= ctrl.exclr;
|
|
|
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode
|
wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode
|
wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure
|
wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure
|
wb_tag_o(2) <= ctrl.src; -- 0 = data access, 1 = instruction access
|
wb_tag_o(2) <= ctrl.src; -- 0 = data access, 1 = instruction access
|
wb_tag_o(3) <= ctrl.excl; -- 1 = exclusive access request
|
|
|
wb_lock_o <= ctrl.lock; -- 1 = exclusive access request
|
|
|
wb_adr_o <= ctrl.adr;
|
wb_adr_o <= ctrl.adr;
|
wb_dat_o <= ctrl.wdat;
|
wb_dat_o <= ctrl.wdat;
|
wb_we_o <= ctrl.we;
|
wb_we_o <= ctrl.we;
|
wb_sel_o <= ctrl.sel;
|
wb_sel_o <= ctrl.sel;
|
