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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
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-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The interface provides registers for all outgoing and for all incoming signals. If the host #
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-- # All bus accesses from the CPU, which do not target the internal IO region / the internal #
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-- # cancels an active transfer, the Wishbone arbiter still waits some time for the bus system to #
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-- # bootloader / the internal instruction or data memories (if implemented), are delegated via #
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-- # ACK/ERR the transfer before the arbiter forces termination. #
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-- # this Wishbone gateway to the external bus interface. Accessed peripherals can have a response #
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-- # latency of up to BUS_TIMEOUT - 1 cycles. #
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-- # #
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-- # #
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-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address #
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-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address #
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-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). #
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-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). #
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-- # #
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-- # #
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-- # All bus accesses from the CPU, which do not target the internal IO region / the internal #
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-- # The interface uses registers for ALL OUTGOING AND FOR ALL INCOMING signals. Hence, an access #
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-- # bootloader / the internal instruction or data memories (if implemented), are delegated via #
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-- # latency of (at least) 2 cycles is added. #
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-- # this Wishbone gateway to the external bus interface. Accessed peripherals can have a response #
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-- # latency of up to BUS_TIMEOUT - 2 cycles. #
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-- # #
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-- # #
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-- # This interface supports classic/standard Wishbone transactions (WB_PIPELINED_MODE = false) #
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-- # This interface supports classic/standard Wishbone transactions (pkg.wb_pipe_mode_c = false) #
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-- # and also pipelined transactions (WB_PIPELINED_MODE = true). #
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-- # and also pipelined transactions (pkg.wb_pipe_mode_c = true). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_wishbone is
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entity neorv32_wishbone is
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generic (
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generic (
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WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
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-- Internal instruction memory --
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-- Internal instruction memory --
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MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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-- Internal data memory --
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-- Internal data memory --
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MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
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signal int_dmem_acc : std_ulogic;
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signal int_dmem_acc : std_ulogic;
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signal int_boot_acc : std_ulogic;
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signal int_boot_acc : std_ulogic;
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signal xbus_access : std_ulogic;
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signal xbus_access : std_ulogic;
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-- bus arbiter
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-- bus arbiter
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type ctrl_state_t is (IDLE, BUSY, RESYNC);
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type ctrl_state_t is (IDLE, BUSY);
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type ctrl_t is record
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type ctrl_t is record
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state : ctrl_state_t;
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state : ctrl_state_t;
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we : std_ulogic;
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we : std_ulogic;
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rd_req : std_ulogic;
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wr_req : std_ulogic;
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adr : std_ulogic_vector(31 downto 0);
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adr : std_ulogic_vector(31 downto 0);
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wdat : std_ulogic_vector(31 downto 0);
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wdat : std_ulogic_vector(31 downto 0);
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rdat : std_ulogic_vector(31 downto 0);
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rdat : std_ulogic_vector(31 downto 0);
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sel : std_ulogic_vector(3 downto 0);
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sel : std_ulogic_vector(03 downto 0);
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ack : std_ulogic;
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ack : std_ulogic;
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err : std_ulogic;
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err : std_ulogic;
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timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
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timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
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src : std_ulogic;
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src : std_ulogic;
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lock : std_ulogic;
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lock : std_ulogic;
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priv : std_ulogic_vector(1 downto 0);
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priv : std_ulogic_vector(01 downto 0);
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end record;
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end record;
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signal ctrl : ctrl_t;
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signal ctrl : ctrl_t;
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signal stb_int : std_ulogic;
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signal stb_int : std_ulogic;
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signal cyc_int : std_ulogic;
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signal cyc_int : std_ulogic;
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signal rdata : std_ulogic_vector(31 downto 0);
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-- async RX mode --
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signal ack_gated : std_ulogic;
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signal rdata_gated : std_ulogic_vector(31 downto 0);
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begin
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- bus timeout --
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-- protocol --
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assert not (BUS_TIMEOUT /= 0) report "NEORV32 PROCESSOR CONFIG NOTE: Using auto-timeout for external bus interface (" & integer'image(BUS_TIMEOUT) & " cycles)." severity note;
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assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing STANDARD Wishbone protocol." severity note;
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assert not (BUS_TIMEOUT = 0) report "NEORV32 PROCESSOR CONFIG NOTE: Using no auto-timeout for external bus interface (might cause permanent CPU stall)." severity note;
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assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing PIEPLINED Wishbone protocol." severity note;
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-- external memory interface protocol + max timeout latency notifier (warning) --
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-- bus timeout --
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assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol." severity note;
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assert not (BUS_TIMEOUT /= 0) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing auto-timeout (" & integer'image(BUS_TIMEOUT) & " cycles)." severity note;
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assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using PIEPLINED Wishbone protocol." severity note;
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assert not (BUS_TIMEOUT = 0) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing no auto-timeout (can cause permanent CPU stall!)." severity note;
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-- endianness --
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-- endianness --
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assert not (xbus_big_endian_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Using LITTLE-ENDIAN byte order for external memory interface." severity note;
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assert not (wb_big_endian_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing LITTLE-endian byte order." severity note;
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assert not (xbus_big_endian_c = true) report "NEORV32 PROCESSOR CONFIG NOTE: Using BIG-ENDIAN byte order for external memory interface." severity note;
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assert not (wb_big_endian_c = true) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing BIG-endian byte." severity note;
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-- async RC --
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assert not (wb_rx_buffer_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing ASYNC RX path." severity note;
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- access to processor-internal IMEM or DMEM? --
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-- access to processor-internal IMEM or DMEM? --
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Line 159... |
-- access to processor-internal BOOTROM or IO devices? --
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-- access to processor-internal BOOTROM or IO devices? --
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int_boot_acc <= '1' when (addr_i(31 downto 16) = boot_rom_base_c(31 downto 16)) else '0'; -- hacky!
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int_boot_acc <= '1' when (addr_i(31 downto 16) = boot_rom_base_c(31 downto 16)) else '0'; -- hacky!
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-- actual external bus access? --
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-- actual external bus access? --
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xbus_access <= (not int_imem_acc) and (not int_dmem_acc) and (not int_boot_acc);
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xbus_access <= (not int_imem_acc) and (not int_dmem_acc) and (not int_boot_acc);
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-- Bus Arbiter -----------------------------------------------------------------------------
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-- Bus Arbiter -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_arbiter: process(rstn_i, clk_i)
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bus_arbiter: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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ctrl.state <= IDLE;
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ctrl.state <= IDLE;
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ctrl.we <= def_rst_val_c;
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ctrl.we <= def_rst_val_c;
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ctrl.rd_req <= '0';
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ctrl.wr_req <= '0';
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ctrl.adr <= (others => def_rst_val_c);
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ctrl.adr <= (others => def_rst_val_c);
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ctrl.wdat <= (others => def_rst_val_c);
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ctrl.wdat <= (others => def_rst_val_c);
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ctrl.rdat <= (others => def_rst_val_c);
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ctrl.rdat <= (others => def_rst_val_c);
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ctrl.sel <= (others => def_rst_val_c);
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ctrl.sel <= (others => def_rst_val_c);
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ctrl.timeout <= (others => def_rst_val_c);
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ctrl.timeout <= (others => def_rst_val_c);
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Line 179... |
ctrl.src <= def_rst_val_c;
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ctrl.src <= def_rst_val_c;
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ctrl.lock <= def_rst_val_c;
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ctrl.lock <= def_rst_val_c;
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ctrl.priv <= (others => def_rst_val_c);
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ctrl.priv <= (others => def_rst_val_c);
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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-- defaults --
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-- defaults --
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ctrl.rdat <= (others => '0');
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ctrl.rdat <= (others => '0'); -- required for internal output gating
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ctrl.ack <= '0';
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ctrl.ack <= '0';
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ctrl.err <= '0';
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ctrl.err <= '0';
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ctrl.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
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ctrl.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
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-- state machine --
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-- state machine --
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case ctrl.state is
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case ctrl.state is
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when IDLE => -- waiting for host request
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when IDLE => -- waiting for host request
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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ctrl.rd_req <= '0';
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ctrl.wr_req <= '0';
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-- buffer all outgoing signals --
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-- buffer all outgoing signals --
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ctrl.we <= wren_i or ctrl.wr_req;
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ctrl.we <= wren_i;
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ctrl.adr <= addr_i;
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ctrl.adr <= addr_i;
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if (xbus_big_endian_c = true) then -- big-endian
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if (wb_big_endian_c = true) then -- big-endian
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ctrl.wdat <= bswap32_f(data_i);
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ctrl.wdat <= bswap32_f(data_i);
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ctrl.sel <= bit_rev_f(ben_i);
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ctrl.sel <= bit_rev_f(ben_i);
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else -- little-endian
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else -- little-endian
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ctrl.wdat <= data_i;
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ctrl.wdat <= data_i;
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ctrl.sel <= ben_i;
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ctrl.sel <= ben_i;
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end if;
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end if;
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ctrl.src <= src_i;
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ctrl.src <= src_i;
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ctrl.lock <= lock_i;
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ctrl.lock <= lock_i;
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ctrl.priv <= priv_i;
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ctrl.priv <= priv_i;
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-- valid new or buffered read/write request --
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-- valid new or buffered read/write request --
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if ((xbus_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then
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if ((xbus_access and (wren_i or rden_i)) = '1') then
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ctrl.state <= BUSY;
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ctrl.state <= BUSY;
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end if;
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end if;
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when BUSY => -- transfer in progress
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when BUSY => -- transfer in progress
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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ctrl.rdat <= wb_dat_i;
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ctrl.rdat <= wb_dat_i;
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if (wb_err_i = '1') then -- abnormal bus termination
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if (wb_err_i = '1') or -- abnormal bus termination
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((timeout_en_c = true) and (or_reduce_f(ctrl.timeout) = '0')) then -- valid timeout
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ctrl.err <= '1';
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ctrl.err <= '1';
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ctrl.state <= IDLE;
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ctrl.state <= IDLE;
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elsif (wb_ack_i = '1') then -- normal bus termination
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elsif (wb_ack_i = '1') then -- normal bus termination
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ctrl.ack <= '1';
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ctrl.ack <= '1';
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ctrl.state <= IDLE;
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ctrl.state <= IDLE;
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elsif (timeout_en_c = true) and (or_reduce_f(ctrl.timeout) = '0') then -- valid timeout
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ctrl.err <= '1';
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ctrl.state <= IDLE;
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end if;
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end if;
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-- timeout counter --
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-- timeout counter --
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if (timeout_en_c = true) then
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if (timeout_en_c = true) then
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ctrl.timeout <= std_ulogic_vector(unsigned(ctrl.timeout) - 1); -- timeout counter
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ctrl.timeout <= std_ulogic_vector(unsigned(ctrl.timeout) - 1); -- timeout counter
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end if;
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end if;
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when RESYNC => -- make sure transfer is done!
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-- ------------------------------------------------------------
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ctrl.wr_req <= ctrl.wr_req or wren_i; -- buffer new request
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ctrl.rd_req <= ctrl.rd_req or rden_i; -- buffer new request
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if (wb_ack_i = '0') then
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ctrl.state <= IDLE;
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end if;
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when others => -- undefined
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when others => -- undefined
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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ctrl.state <= IDLE;
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ctrl.state <= IDLE;
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end case;
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end case;
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end if;
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end if;
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end process bus_arbiter;
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end process bus_arbiter;
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-- host access --
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-- host access --
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data_o <= ctrl.rdat when (xbus_big_endian_c = false) else bswap32_f(ctrl.rdat); -- endianness conversion
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ack_gated <= wb_ack_i when (ctrl.state = BUSY) else '0'; -- CPU ack gate for "async" RX
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ack_o <= ctrl.ack;
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rdata_gated <= wb_dat_i when (ctrl.state = BUSY) else (others => '0'); -- CPU read data gate for "async" RX
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rdata <= ctrl.rdat when (wb_rx_buffer_c = true) else rdata_gated;
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data_o <= rdata when (wb_big_endian_c = false) else bswap32_f(rdata); -- endianness conversion
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ack_o <= ctrl.ack when (wb_rx_buffer_c = true) else ack_gated;
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err_o <= ctrl.err;
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err_o <= ctrl.err;
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-- wishbone interface --
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-- wishbone interface --
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wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode
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wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode
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wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure
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wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure
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| Line 256... |
Line 251... |
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wb_adr_o <= ctrl.adr;
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wb_adr_o <= ctrl.adr;
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wb_dat_o <= ctrl.wdat;
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wb_dat_o <= ctrl.wdat;
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wb_we_o <= ctrl.we;
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wb_we_o <= ctrl.we;
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wb_sel_o <= ctrl.sel;
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wb_sel_o <= ctrl.sel;
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wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int;
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wb_stb_o <= stb_int when (wb_pipe_mode_c = true) else cyc_int;
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wb_cyc_o <= cyc_int;
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wb_cyc_o <= cyc_int;
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stb_int <= '1' when (ctrl.state = BUSY) else '0';
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stb_int <= '1' when (ctrl.state = BUSY) else '0';
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cyc_int <= '0' when (ctrl.state = IDLE) or (ctrl.state = RESYNC) else '1';
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cyc_int <= '1' when (ctrl.state = BUSY) else '0';
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end neorv32_wishbone_rtl;
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end neorv32_wishbone_rtl;
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No newline at end of file
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