| Line 74... |
Line 74... |
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
lock_i : in std_ulogic; -- exclusive access request
|
lock_i : in std_ulogic; -- exclusive access request
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
err_o : out std_ulogic; -- transfer error
|
err_o : out std_ulogic; -- transfer error
|
|
tmo_o : out std_ulogic; -- transfer timeout
|
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
|
priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
|
|
ext_o : out std_ulogic; -- active external access
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
| Line 105... |
Line 107... |
|
|
-- bus arbiter
|
-- bus arbiter
|
type ctrl_state_t is (IDLE, BUSY);
|
type ctrl_state_t is (IDLE, BUSY);
|
type ctrl_t is record
|
type ctrl_t is record
|
state : ctrl_state_t;
|
state : ctrl_state_t;
|
|
state_ff : ctrl_state_t;
|
we : std_ulogic;
|
we : std_ulogic;
|
adr : std_ulogic_vector(31 downto 0);
|
adr : std_ulogic_vector(31 downto 0);
|
wdat : std_ulogic_vector(31 downto 0);
|
wdat : std_ulogic_vector(31 downto 0);
|
rdat : std_ulogic_vector(31 downto 0);
|
rdat : std_ulogic_vector(31 downto 0);
|
sel : std_ulogic_vector(03 downto 0);
|
sel : std_ulogic_vector(03 downto 0);
|
ack : std_ulogic;
|
ack : std_ulogic;
|
err : std_ulogic;
|
err : std_ulogic;
|
|
tmo : std_ulogic;
|
timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
|
timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
|
src : std_ulogic;
|
src : std_ulogic;
|
lock : std_ulogic;
|
lock : std_ulogic;
|
priv : std_ulogic_vector(01 downto 0);
|
priv : std_ulogic_vector(01 downto 0);
|
end record;
|
end record;
|
| Line 164... |
Line 168... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
bus_arbiter: process(rstn_i, clk_i)
|
bus_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
ctrl.state <= IDLE;
|
ctrl.state <= IDLE;
|
|
ctrl.state_ff <= IDLE;
|
ctrl.we <= def_rst_val_c;
|
ctrl.we <= def_rst_val_c;
|
ctrl.adr <= (others => def_rst_val_c);
|
ctrl.adr <= (others => def_rst_val_c);
|
ctrl.wdat <= (others => def_rst_val_c);
|
ctrl.wdat <= (others => def_rst_val_c);
|
ctrl.rdat <= (others => def_rst_val_c);
|
ctrl.rdat <= (others => def_rst_val_c);
|
ctrl.sel <= (others => def_rst_val_c);
|
ctrl.sel <= (others => def_rst_val_c);
|
ctrl.timeout <= (others => def_rst_val_c);
|
ctrl.timeout <= (others => def_rst_val_c);
|
ctrl.ack <= def_rst_val_c;
|
ctrl.ack <= def_rst_val_c;
|
ctrl.err <= def_rst_val_c;
|
ctrl.err <= def_rst_val_c;
|
|
ctrl.tmo <= def_rst_val_c;
|
ctrl.src <= def_rst_val_c;
|
ctrl.src <= def_rst_val_c;
|
ctrl.lock <= def_rst_val_c;
|
ctrl.lock <= def_rst_val_c;
|
ctrl.priv <= (others => def_rst_val_c);
|
ctrl.priv <= (others => def_rst_val_c);
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- defaults --
|
-- defaults --
|
|
ctrl.state_ff <= ctrl.state;
|
ctrl.rdat <= (others => '0'); -- required for internal output gating
|
ctrl.rdat <= (others => '0'); -- required for internal output gating
|
ctrl.ack <= '0';
|
ctrl.ack <= '0';
|
ctrl.err <= '0';
|
ctrl.err <= '0';
|
|
ctrl.tmo <= '0';
|
ctrl.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
|
ctrl.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
|
|
|
-- state machine --
|
-- state machine --
|
case ctrl.state is
|
case ctrl.state is
|
|
|
| Line 208... |
Line 216... |
end if;
|
end if;
|
|
|
when BUSY => -- transfer in progress
|
when BUSY => -- transfer in progress
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl.rdat <= wb_dat_i;
|
ctrl.rdat <= wb_dat_i;
|
if (wb_err_i = '1') or -- abnormal bus termination
|
if (wb_err_i = '1') then -- abnormal bus termination
|
((timeout_en_c = true) and (or_reduce_f(ctrl.timeout) = '0')) then -- valid timeout
|
|
ctrl.err <= '1';
|
ctrl.err <= '1';
|
ctrl.state <= IDLE;
|
ctrl.state <= IDLE;
|
|
elsif (timeout_en_c = true) and (or_reduce_f(ctrl.timeout) = '0') then -- enabled timeout
|
|
ctrl.tmo <= '1';
|
|
ctrl.state <= IDLE;
|
elsif (wb_ack_i = '1') then -- normal bus termination
|
elsif (wb_ack_i = '1') then -- normal bus termination
|
ctrl.ack <= '1';
|
ctrl.ack <= '1';
|
ctrl.state <= IDLE;
|
ctrl.state <= IDLE;
|
end if;
|
end if;
|
-- timeout counter --
|
-- timeout counter --
|
| Line 234... |
Line 244... |
-- host access --
|
-- host access --
|
ack_gated <= wb_ack_i when (ctrl.state = BUSY) else '0'; -- CPU ack gate for "async" RX
|
ack_gated <= wb_ack_i when (ctrl.state = BUSY) else '0'; -- CPU ack gate for "async" RX
|
rdata_gated <= wb_dat_i when (ctrl.state = BUSY) else (others => '0'); -- CPU read data gate for "async" RX
|
rdata_gated <= wb_dat_i when (ctrl.state = BUSY) else (others => '0'); -- CPU read data gate for "async" RX
|
rdata <= ctrl.rdat when (ASYNC_RX = false) else rdata_gated;
|
rdata <= ctrl.rdat when (ASYNC_RX = false) else rdata_gated;
|
|
|
|
ext_o <= '1' when (ctrl.state = BUSY) else '0'; -- active external access
|
|
|
data_o <= rdata when (BIG_ENDIAN = false) else bswap32_f(rdata); -- endianness conversion
|
data_o <= rdata when (BIG_ENDIAN = false) else bswap32_f(rdata); -- endianness conversion
|
ack_o <= ctrl.ack when (ASYNC_RX = false) else ack_gated;
|
ack_o <= ctrl.ack when (ASYNC_RX = false) else ack_gated;
|
err_o <= ctrl.err;
|
err_o <= ctrl.err;
|
|
tmo_o <= ctrl.tmo;
|
|
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_tag_o(0) <= '0' when (ctrl.priv = priv_mode_u_c) else '1'; -- unprivileged access when in user mode
|
wb_tag_o(0) <= '0' when (ctrl.priv = priv_mode_u_c) else '1'; -- unprivileged access when in user mode
|
wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure
|
wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure
|
wb_tag_o(2) <= ctrl.src; -- 0 = data access, 1 = instruction access
|
wb_tag_o(2) <= ctrl.src; -- 0 = data access, 1 = instruction access
|
| Line 252... |
Line 265... |
wb_we_o <= ctrl.we;
|
wb_we_o <= ctrl.we;
|
wb_sel_o <= ctrl.sel;
|
wb_sel_o <= ctrl.sel;
|
wb_stb_o <= stb_int when (PIPE_MODE = true) else cyc_int;
|
wb_stb_o <= stb_int when (PIPE_MODE = true) else cyc_int;
|
wb_cyc_o <= cyc_int;
|
wb_cyc_o <= cyc_int;
|
|
|
stb_int <= '1' when (ctrl.state = BUSY) else '0';
|
stb_int <= '1' when (ctrl.state = BUSY) and (ctrl.state_ff /= BUSY) else '0';
|
cyc_int <= '1' when (ctrl.state = BUSY) else '0';
|
cyc_int <= '1' when (ctrl.state = BUSY) else '0';
|
|
|
|
|
end neorv32_wishbone_rtl;
|
end neorv32_wishbone_rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
