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-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address #
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-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address #
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-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). #
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-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic; -- transfer error
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err_o : out std_ulogic; -- transfer error
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tmo_o : out std_ulogic; -- transfer timeout
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tmo_o : out std_ulogic; -- transfer timeout
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priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
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priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level
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ext_o : out std_ulogic; -- active external access
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ext_o : out std_ulogic; -- active external access
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-- xip configuration --
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xip_en_i : in std_ulogic; -- XIP module enabled
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xip_page_i : in std_ulogic_vector(03 downto 0); -- XIP memory page
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-- wishbone interface --
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-- wishbone interface --
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wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
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wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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-- access control --
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-- access control --
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signal int_imem_acc : std_ulogic;
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signal int_imem_acc : std_ulogic;
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signal int_dmem_acc : std_ulogic;
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signal int_dmem_acc : std_ulogic;
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signal int_boot_acc : std_ulogic;
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signal int_boot_acc : std_ulogic;
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signal xip_acc : std_ulogic;
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signal xbus_access : std_ulogic;
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signal xbus_access : std_ulogic;
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-- bus arbiter
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-- bus arbiter
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type ctrl_state_t is (IDLE, BUSY);
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type ctrl_state_t is (IDLE, BUSY);
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type ctrl_t is record
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type ctrl_t is record
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-- access to processor-internal IMEM or DMEM? --
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-- access to processor-internal IMEM or DMEM? --
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int_imem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) and (MEM_INT_IMEM_EN = true) else '0';
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int_imem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) and (MEM_INT_IMEM_EN = true) else '0';
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int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) and (MEM_INT_DMEM_EN = true) else '0';
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int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) and (MEM_INT_DMEM_EN = true) else '0';
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-- access to processor-internal BOOTROM or IO devices? --
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-- access to processor-internal BOOTROM or IO devices? --
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int_boot_acc <= '1' when (addr_i(31 downto 16) = boot_rom_base_c(31 downto 16)) else '0'; -- hacky!
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int_boot_acc <= '1' when (addr_i(31 downto 16) = boot_rom_base_c(31 downto 16)) else '0'; -- hacky!
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-- XIP access? --
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xip_acc <= '1' when (xip_en_i = '1') and (addr_i(31 downto 28) = xip_page_i) else '0';
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-- actual external bus access? --
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-- actual external bus access? --
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xbus_access <= (not int_imem_acc) and (not int_dmem_acc) and (not int_boot_acc);
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xbus_access <= (not int_imem_acc) and (not int_dmem_acc) and (not int_boot_acc) and (not xip_acc);
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-- Bus Arbiter -----------------------------------------------------------------------------
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-- Bus Arbiter -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_arbiter: process(rstn_i, clk_i)
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bus_arbiter: process(rstn_i, clk_i)
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