| Line 78... |
Line 78... |
signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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-- control registers --
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-- control registers --
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signal irq_enable : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- r/w: interrupt enable
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signal irq_enable : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- r/w: interrupt enable
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signal clr_pending : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- (r)/w: clear/ack pending IRQs
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signal clr_pending : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- r/w: clear pending IRQs
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signal irq_src : std_ulogic_vector(4 downto 0); -- r/w: source IRQ, ACK on any write
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-- interrupt trigger --
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-- interrupt trigger --
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signal irq_sync : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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signal irq_sync : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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signal irq_sync2 : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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signal irq_sync2 : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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signal irq_trig : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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signal irq_trig : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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Line 91... |
-- interrupt buffer --
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-- interrupt buffer --
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signal irq_buf : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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signal irq_buf : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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signal irq_fire : std_ulogic;
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signal irq_fire : std_ulogic;
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-- interrupt source --
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-- interrupt source --
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signal irq_src, irq_src_nxt : std_ulogic_vector(04 downto 0);
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signal irq_src_nxt : std_ulogic_vector(4 downto 0);
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-- arbiter --
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-- arbiter --
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signal irq_run : std_ulogic;
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signal irq_run : std_ulogic;
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signal irq_run_ff : std_ulogic;
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signal host_ack : std_ulogic;
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signal host_ack : std_ulogic;
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begin
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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| Line 120... |
Line 120... |
-- bus handshake --
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-- bus handshake --
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ack_o <= acc_en and (rden_i or wren_i);
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ack_o <= acc_en and (rden_i or wren_i);
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-- write access --
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-- write access --
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host_ack <= '0';
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host_ack <= '0';
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clr_pending <= (others => '0');
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clr_pending <= (others => '1');
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if ((acc_en and wren_i) = '1') then
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if ((acc_en and wren_i) = '1') then
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-- channel-enable --
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-- channel-enable --
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if (addr = xirq_enable_addr_c) then
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if (addr = xirq_enable_addr_c) then
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irq_enable <= data_i(XIRQ_NUM_CH-1 downto 0);
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irq_enable <= data_i(XIRQ_NUM_CH-1 downto 0);
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end if;
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end if;
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-- clear/ACK pending IRQ --
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-- clear pending IRQs --
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if (addr = xirq_pending_addr_c) then
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if (addr = xirq_pending_addr_c) then
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clr_pending <= data_i(XIRQ_NUM_CH-1 downto 0); -- set zero to clear pending IRQ
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end if;
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-- acknowledge IRQ --
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if (addr = xirq_source_addr_c) then -- write _any_ value to ACK
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host_ack <= '1';
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host_ack <= '1';
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clr_pending <= data_i(XIRQ_NUM_CH-1 downto 0);
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end if;
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end if;
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end if;
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end if;
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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Line 181... |
-- IRQ Buffer ---------------------------------------------------------------
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-- IRQ Buffer ---------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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irq_buffer: process(clk_i)
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irq_buffer: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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irq_buf <= (irq_buf or (irq_trig and irq_enable)) and (not clr_pending);
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irq_buf <= (irq_buf or (irq_trig and irq_enable)) and clr_pending;
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end if;
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end if;
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end process irq_buffer;
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end process irq_buffer;
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-- anyone firing? --
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-- anyone firing? --
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irq_fire <= or_reduce_f(irq_buf);
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irq_fire <= or_reduce_f(irq_buf);
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Line 194... |
-- IRQ Priority Encoder -----------------------------------------------------
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-- IRQ Priority Encoder -----------------------------------------------------
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-- -----------------------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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irq_priority: process(irq_buf)
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irq_priority: process(irq_buf)
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begin
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begin
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irq_src_nxt <= (others => '0');
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irq_src_nxt <= (others => '0');
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if (XIRQ_NUM_CH > 1) then
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for i in 0 to XIRQ_NUM_CH-1 loop
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for i in 0 to XIRQ_NUM_CH-1 loop
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if (irq_buf(i) = '1') then
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if (irq_buf(i) = '1') then
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irq_src_nxt <= std_ulogic_vector(to_unsigned(i, 5));
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irq_src_nxt(index_size_f(XIRQ_NUM_CH)-1 downto 0) <= std_ulogic_vector(to_unsigned(i, index_size_f(XIRQ_NUM_CH)));
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exit;
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exit;
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end if;
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end if;
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end loop;
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end loop;
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end if;
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end process irq_priority;
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end process irq_priority;
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-- IRQ Arbiter --------------------------------------------------------------
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-- IRQ Arbiter --------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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irq_arbiter: process(clk_i)
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irq_arbiter: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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irq_run_ff <= irq_run;
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cpu_irq_o <= '0';
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if (irq_run = '0') then -- no active IRQ
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if (irq_run = '0') then -- no active IRQ
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if (irq_fire = '1') then
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if (irq_fire = '1') then
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cpu_irq_o <= '1';
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irq_run <= '1';
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irq_run <= '1';
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irq_src <= irq_src_nxt;
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irq_src <= irq_src_nxt;
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end if;
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end if;
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else -- active IRQ, wait for CPU acknowledge
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else -- active IRQ, wait for CPU to acknowledge
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if (host_ack = '1') then
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if (host_ack = '1') then
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irq_run <= '0';
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irq_run <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process irq_arbiter;
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end process irq_arbiter;
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-- rising-edge detector --
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cpu_irq_o <= irq_run and (not irq_run_ff);
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end neorv32_xirq_rtl;
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end neorv32_xirq_rtl;
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No newline at end of file
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No newline at end of file
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