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-- # << NEORV32 - External Interrupt Controller (XIRQ) >> #
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-- # << NEORV32 - External Interrupt Controller (XIRQ) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Simple interrupt controller for platform (processor-external) interrupts. Up to 32 channels #
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-- # Simple interrupt controller for platform (processor-external) interrupts. Up to 32 channels #
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-- # are supported that get (optionally) prioritized into a single CPU interrupt. #
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-- # are supported that get (optionally) prioritized into a single CPU interrupt. #
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-- # #
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-- # #
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-- # The actual trigger configuration has to be done before synthesis using the XIRQ_TRIGGER_TYPE #
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-- # The actual trigger configuration has to be done BEFORE synthesis using the XIRQ_TRIGGER_TYPE #
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-- # and XIRQ_TRIGGER_POLARITY generics. These allow to configure channel-independent low-level, #
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-- # and XIRQ_TRIGGER_POLARITY generics. These allow to configure channel-independent low-level, #
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-- # high-level, falling-edge and rising-edge triggers. #
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-- # high-level, falling-edge and rising-edge triggers. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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Line 75... |
constant lo_abb_c : natural := index_size_f(xirq_size_c); -- low address boundary bit
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constant lo_abb_c : natural := index_size_f(xirq_size_c); -- low address boundary bit
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal wren : std_ulogic; -- word write enable
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signal rden : std_ulogic; -- read enable
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-- control registers --
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-- control registers --
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signal irq_enable : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- r/w: interrupt enable
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signal irq_enable : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- r/w: interrupt enable
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signal clr_pending : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- r/w: clear pending IRQs
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signal clr_pending : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- r/w: clear pending IRQs
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signal irq_src : std_ulogic_vector(4 downto 0); -- r/w: source IRQ, ACK on any write
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signal irq_src : std_ulogic_vector(4 downto 0); -- r/w: source IRQ, ACK on any write
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-- interrupt source --
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-- interrupt source --
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signal irq_src_nxt : std_ulogic_vector(4 downto 0);
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signal irq_src_nxt : std_ulogic_vector(4 downto 0);
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-- arbiter --
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-- arbiter --
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signal irq_run : std_ulogic;
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signal irq_run : std_ulogic;
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signal host_ack : std_ulogic;
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begin
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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Line 109... |
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = xirq_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = xirq_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= xirq_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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addr <= xirq_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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wren <= acc_en and wren_i;
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rden <= acc_en and rden_i;
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-- Read/Write Access ----------------------------------------------------------------------
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-- Read/Write Access ----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rw_access: process(clk_i)
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rw_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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-- bus handshake --
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-- bus handshake --
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ack_o <= acc_en and (rden_i or wren_i);
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ack_o <= rden or wren;
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-- write access --
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-- write access --
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host_ack <= '0';
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clr_pending <= (others => '1');
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clr_pending <= (others => '1');
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if ((acc_en and wren_i) = '1') then
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if (wren = '1') then
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-- channel-enable --
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-- channel-enable --
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if (addr = xirq_enable_addr_c) then
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if (addr = xirq_enable_addr_c) then
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irq_enable <= data_i(XIRQ_NUM_CH-1 downto 0);
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irq_enable <= data_i(XIRQ_NUM_CH-1 downto 0);
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end if;
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end if;
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-- clear pending IRQs --
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-- clear pending IRQs --
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if (addr = xirq_pending_addr_c) then
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if (addr = xirq_pending_addr_c) then
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clr_pending <= data_i(XIRQ_NUM_CH-1 downto 0); -- set zero to clear pending IRQ
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clr_pending <= data_i(XIRQ_NUM_CH-1 downto 0); -- set zero to clear pending IRQ
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end if;
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end if;
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-- acknowledge IRQ --
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if (addr = xirq_source_addr_c) then -- write _any_ value to ACK
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host_ack <= '1';
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end if;
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end if;
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end if;
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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if ((acc_en and rden_i) = '1') then
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if (rden = '1') then
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case addr is
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case addr is
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when xirq_enable_addr_c => data_o(XIRQ_NUM_CH-1 downto 0) <= irq_enable; -- channel-enable
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when xirq_enable_addr_c => data_o(XIRQ_NUM_CH-1 downto 0) <= irq_enable; -- channel-enable
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when xirq_pending_addr_c => data_o(XIRQ_NUM_CH-1 downto 0) <= irq_buf; -- pending IRQs
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when xirq_pending_addr_c => data_o(XIRQ_NUM_CH-1 downto 0) <= irq_buf; -- pending IRQs
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when xirq_source_addr_c => data_o(4 downto 0) <= irq_src; -- source IRQ
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when xirq_source_addr_c => data_o(4 downto 0) <= irq_src; -- source IRQ
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when others => NULL;
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when others => NULL;
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Line 214... |
if (irq_fire = '1') then
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if (irq_fire = '1') then
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irq_run <= '1';
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irq_run <= '1';
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irq_src <= irq_src_nxt;
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irq_src <= irq_src_nxt;
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end if;
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end if;
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else -- active IRQ, wait for CPU to acknowledge
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else -- active IRQ, wait for CPU to acknowledge
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if (host_ack = '1') then
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if (wren = '1') and (addr = xirq_source_addr_c) then -- write _any_ value to acknowledge
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irq_run <= '0';
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irq_run <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process irq_arbiter;
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end process irq_arbiter;
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