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# SoC/Processor Templates
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# SoC/Processor Templates
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This folder provides exemplary templates that wrap the processor top entity and provide a simplified
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This folder provides exemplary templates that wrap the processor top entity and provide a simplified
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set of configuration generics and IOs. These setups are intended to allow beginner an easy start by
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set of configuration generics and IOs. These setups are intended to allow beginner an easy start by
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hiding much of the processor's configuration complexity. Furthermore, these setups are used by many
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hiding much of the processor's configuration complexity. Furthermore, these setups are used by many
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of the provided [example setups](https://github.com/stnolting/neorv32/tree/master/setups).
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of the provided [example setups](https://github.com/stnolting/neorv32/tree/main/setups).
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Alternatively, you can directly instantiate the processor's top entity
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Alternatively, you can directly instantiate the processor's top entity
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[`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd)
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[`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/core/neorv32_top.vhd)
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to have full access to _all_ features.
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to have full access to _all_ features.
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### [`neorv32_ProcessorTop_Minimal.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd)
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### [`neorv32_ProcessorTop_Minimal.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd)
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This setup used the ["Direct Boot Configuration"](https://stnolting.github.io/neorv32/#_boot_configuration).
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This setup used the ["Direct Boot Configuration"](https://stnolting.github.io/neorv32/#_boot_configuration).
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Application software is installed directly into the processor-internal instruction memory (IMEM) during
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Application software is installed directly into the processor-internal instruction memory (IMEM) during
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synthesis. This memory is implemented as ROM and these is no bootloader available. Hence, the executable
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synthesis. This memory is implemented as ROM and these is no bootloader available. Hence, the executable
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remains unchangeable is executed right after reset.
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remains unchangeable is executed right after reset.
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The setup only provides 3 PWM channels as IO.
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The setup only provides 3 PWM channels as IO.
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### [`neorv32_ProcessorTop_MinimalBoot.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd)
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### [`neorv32_ProcessorTop_MinimalBoot.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd)
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This setup used the ["Indirect Boot Configuration"](https://stnolting.github.io/neorv32/#_boot_configuration).
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This setup used the ["Indirect Boot Configuration"](https://stnolting.github.io/neorv32/#_boot_configuration).
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The NEORV32 bootloader is enabled in this setup allowing to upload new application software at any time
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The NEORV32 bootloader is enabled in this setup allowing to upload new application software at any time
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via a UART connection.
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via a UART connection.
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The setup provides 8 GPIO outputs and the UART communication lines as IO.
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The setup provides 8 GPIO outputs and the UART communication lines as IO.
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### [`neorv32_ProcessorTop_UP5KDemo.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd)
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### [`neorv32_ProcessorTop_UP5KDemo.vhd`](https://github.com/stnolting/neorv32/blob/main/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd)
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This is a more complex template that implements a small microcontroller-like NEORV32.
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This is a more complex template that implements a small microcontroller-like NEORV32.
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It was originally designed for _UPDuino V3_ board, which features a Lattice iCE40up5k FPGA, but has
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It was originally designed for _UPDuino V3_ board, which features a Lattice iCE40up5k FPGA, but has
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also been ported to other boards that provide the same FPGA.
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also been ported to other boards that provide the same FPGA.
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