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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Processor Top Entity with Resolved Port Signals (std_logic/std_logic_vector) >> #
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-- # << NEORV32 - Processor Top Entity with Resolved Port Signals (std_logic/std_logic_vector) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
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IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
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IO_CFS_CONFIG : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic
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IO_CFS_CONFIG : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic
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IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
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IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
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IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
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IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
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IO_NEOLED_EN : boolean := true; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_EN : boolean := true; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_GPTMR_EN : boolean := false -- implement general purpose timer (GPTMR)?
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IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
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IO_XIP_EN : boolean := false -- implement execute in place module (XIP)?
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);
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);
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port (
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port (
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-- Global control --
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-- Global control --
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clk_i : in std_logic := '0'; -- global clock, rising edge
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clk_i : in std_logic := '0'; -- global clock, rising edge
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rstn_i : in std_logic := '0'; -- global reset, low-active, async
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rstn_i : in std_logic := '0'; -- global reset, low-active, async
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wb_ack_i : in std_logic := '0'; -- transfer acknowledge
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wb_ack_i : in std_logic := '0'; -- transfer acknowledge
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wb_err_i : in std_logic := '0'; -- transfer error
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wb_err_i : in std_logic := '0'; -- transfer error
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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fence_o : out std_logic; -- indicates an executed FENCE operation
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fence_o : out std_logic; -- indicates an executed FENCE operation
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fencei_o : out std_logic; -- indicates an executed FENCEI operation
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fencei_o : out std_logic; -- indicates an executed FENCEI operation
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-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
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xip_csn_o : out std_logic; -- chip-select, low-active
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xip_clk_o : out std_logic; -- serial clock
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xip_sdi_i : in std_logic := 'L'; -- device data input
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xip_sdo_o : out std_logic; -- controller data output
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-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
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-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
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slink_tx_dat_o : out sdata_8x32r_t; -- output data
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slink_tx_dat_o : out sdata_8x32r_t; -- output data
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slink_tx_val_o : out std_logic_vector(7 downto 0); -- valid output
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slink_tx_val_o : out std_logic_vector(7 downto 0); -- valid output
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slink_tx_rdy_i : in std_logic_vector(7 downto 0) := (others => '0'); -- ready to send
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slink_tx_rdy_i : in std_logic_vector(7 downto 0) := (others => '0'); -- ready to send
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-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
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-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
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spi_csn_o : out std_logic_vector(07 downto 0); -- SPI CS
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spi_csn_o : out std_logic_vector(07 downto 0); -- SPI CS
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-- TWI (available if IO_TWI_EN = true) --
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-- TWI (available if IO_TWI_EN = true) --
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twi_sda_io : inout std_logic; -- twi serial data line
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twi_sda_io : inout std_logic; -- twi serial data line
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twi_scl_io : inout std_logic; -- twi serial clock line
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twi_scl_io : inout std_logic; -- twi serial clock line
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-- PWM (available if IO_PWM_NUM_CH > 0) --
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-- PWM (available if IO_PWM_NUM_CH > 0) --
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pwm_o : out std_logic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
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pwm_o : out std_logic_vector(59 downto 0); -- pwm channels
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-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
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-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
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cfs_in_i : in std_logic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom inputs
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cfs_in_i : in std_logic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom inputs
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cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom outputs
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cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom outputs
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-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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neoled_o : out std_logic; -- async serial data line
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neoled_o : out std_logic; -- async serial data line
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-- System time --
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-- System time --
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mtime_i : in std_logic_vector(63 downto 0) := (others => '0'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
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mtime_i : in std_logic_vector(63 downto 0) := (others => '0'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
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mtime_o : out std_logic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
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mtime_o : out std_logic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
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-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
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-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
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xirq_i : in std_logic_vector(XIRQ_NUM_CH-1 downto 0) := (others => '0'); -- IRQ channels
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xirq_i : in std_logic_vector(31 downto 0) := (others => '0'); -- IRQ channels
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-- CPU Interrupts --
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-- CPU Interrupts --
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mtime_irq_i : in std_logic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
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mtime_irq_i : in std_logic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
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msw_irq_i : in std_logic := '0'; -- machine software interrupt
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msw_irq_i : in std_logic := '0'; -- machine software interrupt
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mext_irq_i : in std_logic := '0' -- machine external interrupt
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mext_irq_i : in std_logic := '0' -- machine external interrupt
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);
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);
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signal wb_err_i_int : std_ulogic;
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signal wb_err_i_int : std_ulogic;
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--
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--
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signal fence_o_int : std_ulogic;
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signal fence_o_int : std_ulogic;
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signal fencei_o_int : std_ulogic;
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signal fencei_o_int : std_ulogic;
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--
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--
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signal xip_csn_o_int : std_ulogic;
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signal xip_clk_o_int : std_ulogic;
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signal xip_sdi_i_int : std_ulogic;
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signal xip_sdo_o_int : std_ulogic;
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--
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signal slink_tx_dat_o_int : sdata_8x32_t;
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signal slink_tx_dat_o_int : sdata_8x32_t;
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signal slink_tx_val_o_int : std_logic_vector(7 downto 0);
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signal slink_tx_val_o_int : std_logic_vector(7 downto 0);
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signal slink_tx_rdy_i_int : std_logic_vector(7 downto 0);
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signal slink_tx_rdy_i_int : std_logic_vector(7 downto 0);
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signal slink_rx_dat_i_int : sdata_8x32_t;
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signal slink_rx_dat_i_int : sdata_8x32_t;
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signal slink_rx_val_i_int : std_logic_vector(7 downto 0);
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signal slink_rx_val_i_int : std_logic_vector(7 downto 0);
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signal spi_sck_o_int : std_ulogic;
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signal spi_sck_o_int : std_ulogic;
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signal spi_sdo_o_int : std_ulogic;
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signal spi_sdo_o_int : std_ulogic;
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signal spi_sdi_i_int : std_ulogic;
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signal spi_sdi_i_int : std_ulogic;
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signal spi_csn_o_int : std_ulogic_vector(07 downto 0);
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signal spi_csn_o_int : std_ulogic_vector(07 downto 0);
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--
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--
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signal pwm_o_int : std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0);
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signal pwm_o_int : std_ulogic_vector(59 downto 0);
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--
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--
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signal cfs_in_i_int : std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0);
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signal cfs_in_i_int : std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0);
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signal cfs_out_o_int : std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0);
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signal cfs_out_o_int : std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0);
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--
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--
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signal neoled_o_int : std_ulogic;
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signal neoled_o_int : std_ulogic;
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--
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--
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signal mtime_i_int : std_ulogic_vector(63 downto 0);
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signal mtime_i_int : std_ulogic_vector(63 downto 0);
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signal mtime_o_int : std_ulogic_vector(63 downto 0);
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signal mtime_o_int : std_ulogic_vector(63 downto 0);
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--
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--
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signal xirq_i_int : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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signal xirq_i_int : std_ulogic_vector(31 downto 0);
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--
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--
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signal mtime_irq_i_int : std_ulogic;
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signal mtime_irq_i_int : std_ulogic;
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signal msw_irq_i_int : std_ulogic;
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signal msw_irq_i_int : std_ulogic;
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signal mext_irq_i_int : std_ulogic;
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signal mext_irq_i_int : std_ulogic;
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IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)?
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IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)?
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IO_CFS_CONFIG => IO_CFS_CONFIG_INT, -- custom CFS configuration generic
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IO_CFS_CONFIG => IO_CFS_CONFIG_INT, -- custom CFS configuration generic
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IO_CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits
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IO_CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits
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IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, -- size of CFS output conduit in bits
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IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, -- size of CFS output conduit in bits
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IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_GPTMR_EN => IO_GPTMR_EN -- implement general purpose timer (GPTMR)?
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IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)?
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IO_XIP_EN => IO_XIP_EN -- implement execute in place module (XIP)?
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)
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)
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port map (
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port map (
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-- Global control --
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-- Global control --
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clk_i => clk_i_int, -- global clock, rising edge
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clk_i => clk_i_int, -- global clock, rising edge
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rstn_i => rstn_i_int, -- global reset, low-active, async
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rstn_i => rstn_i_int, -- global reset, low-active, async
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wb_ack_i => wb_ack_i_int, -- transfer acknowledge
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wb_ack_i => wb_ack_i_int, -- transfer acknowledge
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wb_err_i => wb_err_i_int, -- transfer error
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wb_err_i => wb_err_i_int, -- transfer error
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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fence_o => fence_o_int, -- indicates an executed FENCE operation
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fence_o => fence_o_int, -- indicates an executed FENCE operation
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fencei_o => fencei_o_int, -- indicates an executed FENCEI operation
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fencei_o => fencei_o_int, -- indicates an executed FENCEI operation
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-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
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xip_csn_o => xip_csn_o_int, -- chip-select, low-active
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xip_clk_o => xip_clk_o_int, -- serial clock
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xip_sdi_i => xip_sdi_i_int, -- device data input
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xip_sdo_o => xip_sdo_o_int, -- controller data output
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-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
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-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
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slink_tx_dat_o => slink_tx_dat_o_int, -- output data
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slink_tx_dat_o => slink_tx_dat_o_int, -- output data
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slink_tx_val_o => slink_tx_val_o_int, -- valid output
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slink_tx_val_o => slink_tx_val_o_int, -- valid output
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slink_tx_rdy_i => slink_tx_rdy_i_int, -- ready to send
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slink_tx_rdy_i => slink_tx_rdy_i_int, -- ready to send
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-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
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-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
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wb_err_i_int <= std_ulogic(wb_err_i);
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wb_err_i_int <= std_ulogic(wb_err_i);
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fence_o <= std_logic(fence_o_int);
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fence_o <= std_logic(fence_o_int);
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fencei_o <= std_logic(fencei_o_int);
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fencei_o <= std_logic(fencei_o_int);
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xip_csn_o <= std_logic(xip_csn_o_int);
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xip_clk_o <= std_logic(xip_clk_o_int);
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xip_sdi_i_int <= std_ulogic(xip_sdi_i);
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xip_sdo_o <= std_logic(xip_sdo_o_int);
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slink_tx_val_o <= std_logic_vector(slink_tx_val_o_int);
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slink_tx_val_o <= std_logic_vector(slink_tx_val_o_int);
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slink_tx_rdy_i_int <= std_ulogic_vector(slink_tx_rdy_i);
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slink_tx_rdy_i_int <= std_ulogic_vector(slink_tx_rdy_i);
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slink_rx_val_i_int <= std_ulogic_vector(slink_rx_val_i);
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slink_rx_val_i_int <= std_ulogic_vector(slink_rx_val_i);
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slink_rx_rdy_o <= std_logic_vector(slink_rx_rdy_o_int);
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slink_rx_rdy_o <= std_logic_vector(slink_rx_rdy_o_int);
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