| Line 4... |
Line 4... |
-- # (c) "AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc. #
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-- # (c) "AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc. #
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-- # Note: External MTIME is not supported. #
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-- # Note: External MTIME is not supported. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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| Line 108... |
Line 108... |
IO_CFS_CONFIG : std_logic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
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IO_CFS_CONFIG : std_logic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
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IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
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IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
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IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
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IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
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IO_NEOLED_EN : boolean := true; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_EN : boolean := true; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
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IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
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IO_GPTMR_EN : boolean := false -- implement general purpose timer (GPTMR)?
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IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
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IO_XIP_EN : boolean := false -- implement execute in place module (XIP)?
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);
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);
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port (
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port (
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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-- AXI4-Lite-Compatible Master Interface --
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-- AXI4-Lite-Compatible Master Interface --
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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| Line 152... |
Line 153... |
jtag_tdo_o : out std_logic; -- serial data output
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jtag_tdo_o : out std_logic; -- serial data output
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jtag_tms_i : in std_logic := '0'; -- mode select
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jtag_tms_i : in std_logic := '0'; -- mode select
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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-- Processor IO --
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-- Processor IO --
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
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xip_csn_o : out std_logic; -- chip-select, low-active
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xip_clk_o : out std_logic; -- serial clock
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xip_sdi_i : in std_logic := 'L'; -- device data input
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xip_sdo_o : out std_logic; -- controller data output
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-- GPIO (available if IO_GPIO_EN = true) --
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-- GPIO (available if IO_GPIO_EN = true) --
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gpio_o : out std_logic_vector(63 downto 0); -- parallel output
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gpio_o : out std_logic_vector(63 downto 0); -- parallel output
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gpio_i : in std_logic_vector(63 downto 0) := (others => '0'); -- parallel input
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gpio_i : in std_logic_vector(63 downto 0) := (others => '0'); -- parallel input
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-- primary UART0 (available if IO_UART0_EN = true) --
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-- primary UART0 (available if IO_UART0_EN = true) --
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uart0_txd_o : out std_logic; -- UART0 send data
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uart0_txd_o : out std_logic; -- UART0 send data
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| Line 174... |
Line 180... |
spi_csn_o : out std_logic_vector(07 downto 0); -- SPI CS
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spi_csn_o : out std_logic_vector(07 downto 0); -- SPI CS
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-- TWI (available if IO_TWI_EN = true) --
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-- TWI (available if IO_TWI_EN = true) --
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twi_sda_io : inout std_logic; -- twi serial data line
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twi_sda_io : inout std_logic; -- twi serial data line
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twi_scl_io : inout std_logic; -- twi serial clock line
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twi_scl_io : inout std_logic; -- twi serial clock line
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-- PWM (available if IO_PWM_NUM_CH > 0) --
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-- PWM (available if IO_PWM_NUM_CH > 0) --
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pwm_o : out std_logic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
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pwm_o : out std_logic_vector(59 downto 0); -- pwm channels
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-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
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-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
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cfs_in_i : in std_logic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom inputs
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cfs_in_i : in std_logic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom inputs
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cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom outputs
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cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom outputs
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-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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neoled_o : out std_logic; -- async serial data line
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neoled_o : out std_logic; -- async serial data line
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-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
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-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
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xirq_i : in std_logic_vector(XIRQ_NUM_CH-1 downto 0) := (others => '0'); -- IRQ channels
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xirq_i : in std_logic_vector(31 downto 0) := (others => '0'); -- IRQ channels
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-- CPU Interrupts --
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-- CPU Interrupts --
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msw_irq_i : in std_logic := '0'; -- machine software interrupt
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msw_irq_i : in std_logic := '0'; -- machine software interrupt
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mext_irq_i : in std_logic := '0' -- machine external interrupt
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mext_irq_i : in std_logic := '0' -- machine external interrupt
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);
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);
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end entity;
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end entity;
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| Line 204... |
Line 210... |
signal jtag_tck_i_int :std_ulogic;
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signal jtag_tck_i_int :std_ulogic;
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signal jtag_tdi_i_int :std_ulogic;
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signal jtag_tdi_i_int :std_ulogic;
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signal jtag_tdo_o_int :std_ulogic;
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signal jtag_tdo_o_int :std_ulogic;
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signal jtag_tms_i_int :std_ulogic;
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signal jtag_tms_i_int :std_ulogic;
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--
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--
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signal xip_csn_o_int : std_ulogic;
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signal xip_clk_o_int : std_ulogic;
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signal xip_sdi_i_int : std_ulogic;
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signal xip_sdo_o_int : std_ulogic;
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--
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signal gpio_o_int : std_ulogic_vector(63 downto 0);
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signal gpio_o_int : std_ulogic_vector(63 downto 0);
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signal gpio_i_int : std_ulogic_vector(63 downto 0);
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signal gpio_i_int : std_ulogic_vector(63 downto 0);
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--
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--
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signal uart0_txd_o_int : std_ulogic;
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signal uart0_txd_o_int : std_ulogic;
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signal uart0_rxd_i_int : std_ulogic;
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signal uart0_rxd_i_int : std_ulogic;
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| Line 222... |
Line 233... |
signal spi_sck_o_int : std_ulogic;
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signal spi_sck_o_int : std_ulogic;
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signal spi_sdo_o_int : std_ulogic;
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signal spi_sdo_o_int : std_ulogic;
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signal spi_sdi_i_int : std_ulogic;
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signal spi_sdi_i_int : std_ulogic;
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signal spi_csn_o_int : std_ulogic_vector(07 downto 0);
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signal spi_csn_o_int : std_ulogic_vector(07 downto 0);
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--
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--
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signal pwm_o_int : std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0);
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signal pwm_o_int : std_ulogic_vector(59 downto 0);
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--
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--
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signal cfs_in_i_int : std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0);
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signal cfs_in_i_int : std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0);
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signal cfs_out_o_int : std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0);
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signal cfs_out_o_int : std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0);
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--
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--
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signal neoled_o_int : std_ulogic;
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signal neoled_o_int : std_ulogic;
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--
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--
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signal xirq_i_int : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0);
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signal xirq_i_int : std_ulogic_vector(31 downto 0);
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--
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--
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signal msw_irq_i_int : std_ulogic;
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signal msw_irq_i_int : std_ulogic;
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signal mext_irq_i_int : std_ulogic;
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signal mext_irq_i_int : std_ulogic;
|
|
|
-- internal wishbone bus --
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-- internal wishbone bus --
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| Line 341... |
Line 352... |
IO_CFS_CONFIG => IO_CFS_CONFIG_INT, -- custom CFS configuration generic
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IO_CFS_CONFIG => IO_CFS_CONFIG_INT, -- custom CFS configuration generic
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IO_CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits
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IO_CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits
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IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, -- size of CFS output conduit in bits
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IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, -- size of CFS output conduit in bits
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IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_TX_FIFO => IO_NEOLED_TX_FIFO, -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
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IO_NEOLED_TX_FIFO => IO_NEOLED_TX_FIFO, -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
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IO_GPTMR_EN => IO_GPTMR_EN -- implement general purpose timer (GPTMR)?
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IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)?
|
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IO_XIP_EN => IO_XIP_EN -- implement execute in place module (XIP)?
|
)
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)
|
port map (
|
port map (
|
-- Global control --
|
-- Global control --
|
clk_i => clk_i_int, -- global clock, rising edge
|
clk_i => clk_i_int, -- global clock, rising edge
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rstn_i => rstn_i_int, -- global reset, low-active, async
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rstn_i => rstn_i_int, -- global reset, low-active, async
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| Line 368... |
Line 380... |
wb_ack_i => wb_core.ack, -- transfer acknowledge
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wb_ack_i => wb_core.ack, -- transfer acknowledge
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wb_err_i => wb_core.err, -- transfer error
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wb_err_i => wb_core.err, -- transfer error
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
fence_o => open, -- indicates an executed FENCE operation
|
fence_o => open, -- indicates an executed FENCE operation
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fencei_o => open, -- indicates an executed FENCEI operation
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fencei_o => open, -- indicates an executed FENCEI operation
|
|
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
|
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xip_csn_o => xip_csn_o_int, -- chip-select, low-active
|
|
xip_clk_o => xip_clk_o_int, -- serial clock
|
|
xip_sdi_i => xip_sdi_i_int, -- device data input
|
|
xip_sdo_o => xip_sdo_o_int, -- controller data output
|
-- GPIO (available if IO_GPIO_EN = true) --
|
-- GPIO (available if IO_GPIO_EN = true) --
|
gpio_o => gpio_o_int, -- parallel output
|
gpio_o => gpio_o_int, -- parallel output
|
gpio_i => gpio_i_int, -- parallel input
|
gpio_i => gpio_i_int, -- parallel input
|
-- primary UART0 (available if IO_UART0_EN = true) --
|
-- primary UART0 (available if IO_UART0_EN = true) --
|
uart0_txd_o => uart0_txd_o_int, -- UART0 send data
|
uart0_txd_o => uart0_txd_o_int, -- UART0 send data
|
| Line 408... |
Line 425... |
msw_irq_i => msw_irq_i_int, -- machine software interrupt
|
msw_irq_i => msw_irq_i_int, -- machine software interrupt
|
mext_irq_i => mext_irq_i_int -- machine external interrupt
|
mext_irq_i => mext_irq_i_int -- machine external interrupt
|
);
|
);
|
|
|
-- type conversion --
|
-- type conversion --
|
|
xip_csn_o <= std_logic(xip_csn_o_int);
|
|
xip_clk_o <= std_logic(xip_clk_o_int);
|
|
xip_sdi_i_int <= std_ulogic(xip_sdi_i);
|
|
xip_sdo_o <= std_logic(xip_sdo_o_int);
|
|
|
gpio_o <= std_logic_vector(gpio_o_int);
|
gpio_o <= std_logic_vector(gpio_o_int);
|
gpio_i_int <= std_ulogic_vector(gpio_i);
|
gpio_i_int <= std_ulogic_vector(gpio_i);
|
|
|
jtag_trst_i_int <= std_ulogic(jtag_trst_i);
|
jtag_trst_i_int <= std_ulogic(jtag_trst_i);
|
jtag_tck_i_int <= std_ulogic(jtag_tck_i);
|
jtag_tck_i_int <= std_ulogic(jtag_tck_i);
|
