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This folder contains a script for simulating the processor using GHDL.This folder contains a script for simulating the processor using GHDL.
### [`rtl_modules`](https://github.com/stnolting/neorv32/tree/master/sim/rtl_modules)### [`rtl_modules`](https://github.com/stnolting/neorv32/tree/master/sim/rtl_modules)
This folder provides additional/alternative simulation components. The the comments in the according files for more information.This folder provides additional/alternative simulation components (mainly optimized memory components yet). See the comments in the according files for more information.
### [`vivado`](https://github.com/stnolting/neorv32/tree/master/sim/vivado)### [`vivado`](https://github.com/stnolting/neorv32/tree/master/sim/vivado)
This folder provides an example waveform configuration (for Xilinx ISIM simulator) for the default testbench.This folder provides an example waveform configuration (for Xilinx ISIM simulator) for the default testbench.
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