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## Simulation Source Folder
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# Simulation Source Folder
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### [`ghdl`](https://github.com/stnolting/neorv32/tree/master/sim/ghdl)
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This folder contains a script for simulating the processor using GHDL.
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## [`neorv32_tb.simple.vhd`](neorv32_tb.simple.vhd) and [`ghdl_sim.sh`](ghdl_sim)
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### [`rtl_modules`](https://github.com/stnolting/neorv32/tree/master/sim/rtl_modules)
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Simple testbench for the NEORV32 Processor and script for simulation using GHDL.
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## [`rtl_modules`](rtl_modules)
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This folder provides additional/alternative simulation components (mainly optimized memory components yet). See the comments in the according files for more information.
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This folder provides additional/alternative simulation components (mainly optimized memory components yet). See the comments in the according files for more information.
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### [`neorv32_tb.vhd`](https://github.com/stnolting/neorv32/tree/master/sim/neorv32_tb.vhd)
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VUnit testbench for the NEORV32 Processor.
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## [`neorv32_tb.vhd`](neorv32_tb.vhd) and [`run.py`](run.py)
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VUnit testbench and run script for the NEORV32 Processor.
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## [`run_riscv_arch_test.sh`](run_riscv_arch_test.sh): NEORV32 RISC-V Architecture Test Framework
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This script tests the NEORV32 Processor for RISC-V compatibility using the
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[official RISC-V architecture test suite v2+](https://github.com/riscv/riscv-arch-test).
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The core's HDL sources are *simulated* using `GHDL` to provide a virtual execution platform for the test framework:
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* `rv32i_m/C` - compressed instructions
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* `rv32i_m/I` - base ISA
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* `rv32i_m/M` - hardware integer multiplication and division
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* `rv32i_m/privilege` - privileged architecture
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* `rv32i_m/Zifencei` - instruction stream synchronization (for example for self-modifying code)
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:warning: The RISC-V GCC toolchain (`riscv{32|64}-unknown-elf`) is required for program compilation, and the simulation
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depends on `ghdl_sim.sh`.
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To execute all the supported tests open a terminal and run [`./sim/run_riscv_arch_test.sh`](run_riscv_arch_test.sh),
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which does the following:
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* Make local copies of the NEORV32 `rtl`, `sim` and `sw` folders in `work/`, to keep the project's core files clean.
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* Clone (as `git submodule`) the [riscv-arch-test repository](https://github.com/riscv/riscv-arch-test) into `sw/isa-test/riscv-arch-test`.
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* Install (copy) the custom `neorv32` test target from `sw/isa-test/port-neorv32` to the
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test suite's target folder `work/riscv-arch-test/riscv-target/neorv32`
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* Make a copy of the original IMEM VHDL source file of the processor (`cp work/neorv32/rtl/core/neorv32_imem.vhd work/neorv32/rtl/core/neorv32_imem.ORIGINAL`);
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since the IMEM will be overriden by the device makefiles with a simulation-optimized one (`neorv32/sim/rtl_modules/neorv32_imem.vhd`).
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Still, the original IMEM is required for certain tests that use self-modifying code.
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* Run the actual tests.
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:warning: Simulating all the test cases takes quite some time.
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### [`neorv32_tb.simple.vhd`](https://github.com/stnolting/neorv32/tree/master/sim/neorv32_tb.simple.vhd)
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:warning: If the simulation of a test does not generate any signature output at all or if the signature is truncated,
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try increasing the simulation time by modiying the `SIM_TIME` variable when calling the test makefiles in `run_riscv_arch_test.sh`.
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Simple testbench for the NEORV32 Processor.
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More datails regarding the actual simulation process can be found in the
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[target's `README`](../sw/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/README.md).
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