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# Simulation Source Folder
# Simulation Source Folder
 
 
 
 
## [`neorv32_tb.simple.vhd`](neorv32_tb.simple.vhd) and [`ghdl_sim.sh`](ghdl_sim)
## [simple](simple)
 
 
Simple testbench for the NEORV32 Processor and script for simulation using GHDL.
Simple testbench for the NEORV32 Processor and script for simulation using GHDL.
 
 
 
- [`ghdl.setup.sh`](simple/ghdl.setup.sh)
## [`rtl_modules`](rtl_modules)
- [`ghdl.run.sh`](simple/ghdl.run.sh)
 
- [`ghdl.sh`](simple/ghdl.sh)
This folder provides additional/alternative simulation components (mainly optimized memory components yet). See the comments in the according files for more information.
- [`neorv32_tb.simple.vhd`](simple/neorv32_tb.simple.vhd)
 
- [`neorv32_imem.simple.vhd`](simple/neorv32_imem.simple.vhd): memory component optimized for simulation.
 
- [`neorv32_imem.iram.simple.vhd`](simple/neorv32_imem.iram.simple.vhd)
## [`neorv32_tb.vhd`](neorv32_tb.vhd) and [`run.py`](run.py)
- [`uart_rx.simple.vhd`](simple/uart_rx.simple.vhd)
 
 
VUnit testbench and run script for the NEORV32 Processor.
 
 
## VUnit testbench
 
 
 
VUnit testbench for the NEORV32 Processor.
 
 
 
- [`run.py`](run.py)
 
- [`neorv32_tb.vhd`](neorv32_tb.vhd)
 
- [`uart_rx_pkg.vhd`](uart_rx_pkg.vhd)
 
- [`uart_rx.vhd`](uart_rx.vhd)
 
 
 
 
## [`run_riscv_arch_test.sh`](run_riscv_arch_test.sh): NEORV32 RISC-V Architecture Test Framework
## [`run_riscv_arch_test.sh`](run_riscv_arch_test.sh): NEORV32 RISC-V Architecture Test Framework
 
 
This script tests the NEORV32 Processor for RISC-V compatibility using the
This script tests the NEORV32 Processor for RISC-V compatibility using the
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* `rv32i_m/M` - hardware integer multiplication and division
* `rv32i_m/M` - hardware integer multiplication and division
* `rv32i_m/privilege` - privileged architecture
* `rv32i_m/privilege` - privileged architecture
* `rv32i_m/Zifencei` - instruction stream synchronization (for example for self-modifying code)
* `rv32i_m/Zifencei` - instruction stream synchronization (for example for self-modifying code)
 
 
:warning: The RISC-V GCC toolchain (`riscv{32|64}-unknown-elf`) is required for program compilation, and the simulation
:warning: The RISC-V GCC toolchain (`riscv{32|64}-unknown-elf`) is required for program compilation, and the simulation
depends on `ghdl_sim.sh`.
  depends on `simple/ghdl_sim.sh`.
 
 
To execute all the supported tests open a terminal and run [`./sim/run_riscv_arch_test.sh`](run_riscv_arch_test.sh),
To execute all the supported tests open a terminal and run [`./sim/run_riscv_arch_test.sh`](run_riscv_arch_test.sh),
which does the following:
which does the following:
 
 
* Make local copies of the NEORV32 `rtl`, `sim` and `sw` folders in `work/`, to keep the project's core files clean.
* Make a local copy of the NEORV32 `rtl` folder in `work/`, to keep the project's core files clean.
* Clone (as `git submodule`) the [riscv-arch-test repository](https://github.com/riscv/riscv-arch-test) into `sw/isa-test/riscv-arch-test`.
* Clone (as `git submodule`) the [riscv-arch-test repository](https://github.com/riscv/riscv-arch-test) into `sw/isa-test/riscv-arch-test`.
* Install (copy) the custom `neorv32` test target from `sw/isa-test/port-neorv32` to the
* Install (copy) the custom `neorv32` test target from `sw/isa-test/port-neorv32` to the
test suite's target folder `work/riscv-arch-test/riscv-target/neorv32`
test suite's target folder `work/riscv-arch-test/riscv-target/neorv32`.
* Make a copy of the original IMEM VHDL source file of the processor (`cp work/neorv32/rtl/core/neorv32_imem.vhd work/neorv32/rtl/core/neorv32_imem.ORIGINAL`);
 
  since the IMEM will be overriden by the device makefiles with a simulation-optimized one (`neorv32/sim/rtl_modules/neorv32_imem.vhd`).
 
  Still, the original IMEM is required for certain tests that use self-modifying code.
 
* Run the actual tests.
* Run the actual tests.
 
 
:warning: Simulating all the test cases takes quite some time.
:warning: Simulating all the test cases takes quite some time. Some tests use an optimised description of IMEM
 
  (`neorv32_imem.simple.vhd`), but others require the original because they execute self-modifying code.
 
 
:warning: If the simulation of a test does not generate any signature output at all or if the signature is truncated,
:warning: If the simulation of a test does not generate any signature output at all or if the signature is truncated,
try increasing the simulation time by modiying the `SIM_TIME` variable when calling the test makefiles in `run_riscv_arch_test.sh`.
try increasing the simulation time by modiying the `SIM_TIME` variable when calling the test makefiles in `run_riscv_arch_test.sh`.
 
 
More datails regarding the actual simulation process can be found in the
More datails regarding the actual simulation process can be found in the

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