| Line 58... |
Line 58... |
constant f_clock_c : real := 100000000.0; -- main clock in Hz
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constant f_clock_c : real := 100000000.0; -- main clock in Hz
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constant f_clock_nat_c : natural := 100000000; -- main clock in Hz
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constant f_clock_nat_c : natural := 100000000; -- main clock in Hz
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constant baud_rate_c : real := 19200.0; -- standard UART baudrate
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constant baud_rate_c : real := 19200.0; -- standard UART baudrate
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constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address
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constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address
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constant wb_mem_size_c : natural := 256; -- wishbone memory size in bytes
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constant wb_mem_size_c : natural := 256; -- wishbone memory size in bytes
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constant wb_mem_latency_c : natural := 8; -- latency in clock cycles (min 1)
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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|
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-- text.io --
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-- text.io --
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file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
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file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
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| Line 101... |
Line 102... |
ack : std_ulogic; -- transfer acknowledge
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ack : std_ulogic; -- transfer acknowledge
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err : std_ulogic; -- transfer error
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err : std_ulogic; -- transfer error
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end record;
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end record;
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signal wb_cpu : wishbone_t;
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signal wb_cpu : wishbone_t;
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|
|
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-- Wishbone memory --
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-- Wishbone memory, SimCom --
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type wb_mem_ram_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type wb_mem_file_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type wb_mem_read_latency_t is array (0 to wb_mem_latency_c-1) of std_ulogic_vector(31 downto 0);
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signal wb_mem_file : wb_mem_file_t := (others => (others => '0'));
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type wb_mem_t is record
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signal rb_en : std_ulogic;
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ram : wb_mem_ram_t;
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signal r_data : std_ulogic_vector(31 downto 0);
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rdata : wb_mem_read_latency_t;
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signal wb_acc_en : std_ulogic;
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acc_en : std_ulogic;
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signal wb_mem_rdata : std_ulogic_vector(31 downto 0);
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ack : std_ulogic_vector(wb_mem_latency_c-1 downto 0);
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signal wb_mem_ack : std_ulogic;
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rb_en : std_ulogic_vector(wb_mem_latency_c-1 downto 0);
|
|
end record;
|
|
signal wb_mem : wb_mem_t;
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|
|
begin
|
begin
|
|
|
-- Clock/Reset Generator ------------------------------------------------------------------
|
-- Clock/Reset Generator ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
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| Line 135... |
Line 138... |
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
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CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
|
-- Extension Options --
|
-- Extension Options --
|
CSR_COUNTERS_USE => true, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
|
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
|
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_USE => true, -- implement PMP?
|
PMP_USE => true, -- implement PMP?
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PMP_NUM_REGIONS => 4, -- number of regions (max 16)
|
PMP_NUM_REGIONS => 4, -- number of regions (max 16)
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PMP_GRANULARITY => 14, -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
PMP_GRANULARITY => 14, -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
-- Memory configuration: Instruction memory --
|
-- Internal Instruction memory --
|
MEM_ISPACE_BASE => x"00000000", -- base address of instruction memory space
|
|
MEM_ISPACE_SIZE => 16*1024, -- total size of instruction memory space in byte
|
|
MEM_INT_IMEM_USE => true, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_USE => true, -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
|
MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
|
-- Memory configuration: Data memory --
|
-- Internal Data memory --
|
MEM_DSPACE_BASE => x"80000000", -- base address of data memory space
|
|
MEM_DSPACE_SIZE => 8*1024, -- total size of data memory space in byte
|
|
MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
|
MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
|
-- Memory configuration: External memory interface --
|
-- External memory interface --
|
MEM_EXT_USE => true, -- implement external memory bus interface?
|
MEM_EXT_USE => true, -- implement external memory bus interface?
|
MEM_EXT_REG_STAGES => 2, -- number of interface register stages (0,1,2)
|
MEM_EXT_REG_STAGES => 2, -- number of interface register stages (0,1,2)
|
MEM_EXT_TIMEOUT => 15, -- cycles after which a valid bus access will timeout
|
MEM_EXT_TIMEOUT => 15, -- cycles after which a valid bus access will timeout
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
|
| Line 164... |
Line 162... |
IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_SPI_USE => true, -- implement serial peripheral interface (SPI)?
|
IO_SPI_USE => true, -- implement serial peripheral interface (SPI)?
|
IO_TWI_USE => true, -- implement two-wire interface (TWI)?
|
IO_TWI_USE => true, -- implement two-wire interface (TWI)?
|
IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_USE => true, -- implement watch dog timer (WDT)?
|
IO_WDT_USE => true, -- implement watch dog timer (WDT)?
|
IO_TRNG_USE => false, -- CANNOT BE SIMULATED!
|
IO_TRNG_USE => false, -- DEFAULT TRNG CONFIG CANNOT BE SIMULATED!
|
IO_DEVNULL_USE => true -- implement dummy device (DEVNULL)?
|
IO_DEVNULL_USE => true, -- implement dummy device (DEVNULL)?
|
|
IO_CFU_USE => true -- implement custom functions unit (CFU)?
|
)
|
)
|
port map (
|
port map (
|
-- Global control --
|
-- Global control --
|
clk_i => clk_gen, -- global clock, rising edge
|
clk_i => clk_gen, -- global clock, rising edge
|
rstn_i => rst_gen, -- global reset, low-active, async
|
rstn_i => rst_gen, -- global reset, low-active, async
|
| Line 208... |
Line 207... |
|
|
-- TWI termination --
|
-- TWI termination --
|
twi_scl <= 'H';
|
twi_scl <= 'H';
|
twi_sda <= 'H';
|
twi_sda <= 'H';
|
|
|
-- Wishbone read-back --
|
|
wb_cpu.rdata <= wb_mem_rdata;
|
|
wb_cpu.ack <= wb_mem_ack;
|
|
wb_cpu.err <= '0';
|
|
|
|
|
|
-- Console UART Receiver ------------------------------------------------------------------
|
-- Console UART Receiver ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
uart_rx_console: process(clk_gen)
|
uart_rx_console: process(clk_gen)
|
variable i : integer;
|
variable i : integer;
|
| Line 268... |
Line 262... |
end process uart_rx_console;
|
end process uart_rx_console;
|
|
|
|
|
-- Wishbone Memory ------------------------------------------------------------------------
|
-- Wishbone Memory ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
wb_mem_file_access: process(clk_gen)
|
wb_mem_ram_access: process(clk_gen)
|
begin
|
begin
|
if rising_edge(clk_gen) then
|
if rising_edge(clk_gen) then
|
rb_en <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en and (not wb_cpu.we); -- read-back control
|
-- control --
|
wb_mem_ack <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en; -- wishbone acknowledge
|
wb_mem.rb_en(0) <= wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en and (not wb_cpu.we); -- read-back control
|
if ((wb_cpu.cyc and wb_cpu.stb and wb_acc_en and wb_cpu.we) = '1') then -- valid write access
|
wb_mem.ack(0) <= wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en; -- wishbone acknowledge
|
|
-- write access --
|
|
if ((wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en and wb_cpu.we) = '1') then -- valid write access
|
for i in 0 to 3 loop
|
for i in 0 to 3 loop
|
if (wb_cpu.sel(i) = '1') then
|
if (wb_cpu.sel(i) = '1') then
|
wb_mem_file(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_cpu.wdata(7+i*8 downto 0+i*8);
|
wb_mem.ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_cpu.wdata(7+i*8 downto 0+i*8);
|
end if;
|
end if;
|
end loop; -- i
|
end loop; -- i
|
end if;
|
end if;
|
r_data <= wb_mem_file(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned
|
-- read access --
|
end if;
|
wb_mem.rdata(0) <= wb_mem.ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned
|
end process wb_mem_file_access;
|
-- virtual read and ack latency --
|
|
if (wb_mem_latency_c > 1) then
|
-- wb mem access --
|
for i in 1 to wb_mem_latency_c-1 loop
|
wb_acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0';
|
wb_mem.rdata(i) <= wb_mem.rdata(i-1);
|
|
wb_mem.rb_en(i) <= wb_mem.rb_en(i-1);
|
-- output gate --
|
wb_mem.ack(i) <= wb_mem.ack(i-1);
|
wb_mem_rdata <= r_data when (rb_en = '1') else (others=> '0');
|
end loop;
|
|
end if;
|
|
end if;
|
|
end process wb_mem_ram_access;
|
|
|
|
-- wishbone memory access? --
|
|
wb_mem.acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0';
|
|
|
|
-- output to cpu --
|
|
wb_cpu.rdata <= wb_mem.rdata(wb_mem_latency_c-1) when (wb_mem.rb_en(wb_mem_latency_c-1) = '1') else (others=> '0'); -- data output gate
|
|
wb_cpu.ack <= wb_mem.ack(wb_mem_latency_c-1);
|
|
wb_cpu.err <= '0';
|
|
|
|
|
end neorv32_tb_rtl;
|
end neorv32_tb_rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
