| Line 1... |
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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Simple Testbench with UART-to-Console module >> #
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-- # << NEORV32 - Simple Testbench >> #
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-- # ********************************************************************************************* #
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-- # This testbench provides a virtual UART receiver connected to the processor's uart_txd_o #
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-- # signals. The received chars are shown in the simulator console and also written to a file #
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-- # ("neorv32.testbench_uart.out"). #
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-- # Futhermore, this testbench provides a simple RAM connected to the external Wishbone bus. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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| Line 50... |
Line 55... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant t_clock_c : time := 10 ns; -- main clock period
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constant t_clock_c : time := 10 ns; -- main clock period
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constant f_clock_c : real := 100000000.0; -- main clock in Hz
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constant f_clock_c : real := 100000000.0; -- main clock in Hz
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constant f_clock_nat_c : natural := 100000000; -- main clock in Hz
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constant f_clock_nat_c : natural := 100000000; -- main clock in Hz
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constant baud_rate_c : real := 19200.0; -- standard UART baudrate
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constant baud_rate_c : real := 19200.0; -- standard UART baudrate
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constant wb_mem_size_c : natural := 256; -- wishbone memory size in bytes
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constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address
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constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address
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constant wb_mem_size_c : natural := 256; -- wishbone memory size in bytes
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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|
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-- textio --
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-- text.io --
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file file_uart_tx_out : text open write_mode is "neorv32.sim_uart.out";
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file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
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|
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-- internal configuration --
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-- internal configuration --
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constant baud_val_c : real := f_clock_c / baud_rate_c;
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constant baud_val_c : real := f_clock_c / baud_rate_c;
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constant f_clk_c : natural := natural(f_clock_c);
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constant f_clk_c : natural := natural(f_clock_c);
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|
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-- reduced ASCII table --
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-- generators --
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type ascii_t is array (0 to 94) of character;
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signal clk_gen, rst_gen : std_ulogic := '0';
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constant ascii_lut : ascii_t := (' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-',
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'.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?', '@', 'A',
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-- simulation uart receiver --
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'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U',
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signal uart_txd : std_ulogic;
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'V', 'W', 'X', 'Y', 'Z', '[', '\', ']', '^', '_', '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i',
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signal uart_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '{', '|', '}', '~');
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signal uart_rx_busy : std_ulogic := '0';
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signal uart_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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-- generators --
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signal uart_rx_baud_cnt : real;
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signal clk_gen, rst_gen : std_ulogic := '0';
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signal uart_rx_bitcnt : natural;
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|
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-- simulation uart receiver --
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-- gpio --
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signal uart_txd : std_ulogic;
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signal gpio : std_ulogic_vector(15 downto 0);
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signal uart_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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signal uart_rx_busy : std_ulogic := '0';
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-- twi --
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signal uart_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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signal twi_scl, twi_sda : std_logic;
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signal uart_rx_baud_cnt : real;
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signal uart_rx_bitcnt : natural;
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-- spi --
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signal spi_data : std_logic;
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-- gpio --
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signal gpio : std_ulogic_vector(15 downto 0);
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-- Wishbone bus --
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type wishbone_t is record
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-- twi --
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addr : std_ulogic_vector(31 downto 0); -- address
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signal twi_scl, twi_sda : std_logic;
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wdata : std_ulogic_vector(31 downto 0); -- master write data
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|
rdata : std_ulogic_vector(31 downto 0); -- master read data
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-- spi --
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we : std_ulogic; -- write enable
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signal spi_data : std_logic;
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sel : std_ulogic_vector(03 downto 0); -- byte enable
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|
stb : std_ulogic; -- strobe
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-- Wishbone bus --
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cyc : std_ulogic; -- valid cycle
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type wishbone_t is record
|
ack : std_ulogic; -- transfer acknowledge
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addr : std_ulogic_vector(31 downto 0); -- address
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err : std_ulogic; -- transfer error
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wdata : std_ulogic_vector(31 downto 0); -- master write data
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end record;
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rdata : std_ulogic_vector(31 downto 0); -- master read data
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signal wb_cpu : wishbone_t;
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we : std_ulogic; -- write enable
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sel : std_ulogic_vector(03 downto 0); -- byte enable
|
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stb : std_ulogic; -- strobe
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-- Wishbone memory, SimCom --
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cyc : std_ulogic; -- valid cycle
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type wb_mem_file_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0);
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ack : std_ulogic; -- transfer acknowledge
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signal wb_mem_file : wb_mem_file_t := (others => (others => '0'));
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err : std_ulogic; -- transfer error
|
signal rb_en : std_ulogic;
|
end record;
|
signal r_data : std_ulogic_vector(31 downto 0);
|
signal wb_cpu : wishbone_t;
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signal wb_acc_en : std_ulogic;
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signal wb_mem_rdata : std_ulogic_vector(31 downto 0);
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signal wb_mem_ack : std_ulogic;
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-- Wishbone memory --
|
|
type wb_mem_file_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0);
|
begin
|
signal wb_mem_file : wb_mem_file_t := (others => (others => '0'));
|
|
signal rb_en : std_ulogic;
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-- Clock/Reset Generator ------------------------------------------------------------------
|
signal r_data : std_ulogic_vector(31 downto 0);
|
-- -------------------------------------------------------------------------------------------
|
signal wb_acc_en : std_ulogic;
|
clk_gen <= not clk_gen after (t_clock_c/2);
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|
rst_gen <= '0', '1' after 60*(t_clock_c/2);
|
begin
|
|
|
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-- Clock/Reset Generator ------------------------------------------------------------------
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-- CPU Core -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
clk_gen <= not clk_gen after (t_clock_c/2);
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neorv32_top_inst: neorv32_top
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rst_gen <= '0', '1' after 60*(t_clock_c/2);
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generic map (
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|
-- General --
|
|
CLOCK_FREQUENCY => f_clock_nat_c, -- clock frequency of clk_i in Hz
|
-- CPU Core -------------------------------------------------------------------------------
|
HART_ID => x"ABCD1234", -- custom hardware thread ID
|
-- -------------------------------------------------------------------------------------------
|
BOOTLOADER_USE => false, -- implement processor-internal bootloader?
|
neorv32_top_inst: neorv32_top
|
-- RISC-V CPU Extensions --
|
generic map (
|
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
|
-- General --
|
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
|
CLOCK_FREQUENCY => f_clock_nat_c, -- clock frequency of clk_i in Hz
|
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
|
HART_ID => x"ABCD1234", -- custom hardware thread ID
|
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
|
BOOTLOADER_USE => false, -- implement processor-internal bootloader?
|
-- Memory configuration: Instruction memory --
|
-- RISC-V CPU Extensions --
|
MEM_ISPACE_BASE => x"00000000", -- base address of instruction memory space
|
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
|
MEM_ISPACE_SIZE => 16*1024, -- total size of instruction memory space in byte
|
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
|
MEM_INT_IMEM_USE => true, -- implement processor-internal instruction memory
|
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
|
MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes
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CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
|
MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
|
-- Memory configuration: Instruction memory --
|
-- Memory configuration: Data memory --
|
MEM_ISPACE_BASE => x"00000000", -- base address of instruction memory space
|
MEM_DSPACE_BASE => x"80000000", -- base address of data memory space
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MEM_ISPACE_SIZE => 16*1024, -- total size of instruction memory space in byte
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MEM_DSPACE_SIZE => 8*1024, -- total size of data memory space in byte
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MEM_INT_IMEM_USE => true, -- implement processor-internal instruction memory
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MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
|
MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes
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MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
|
MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
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-- Memory configuration: External memory interface --
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-- Memory configuration: Data memory --
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MEM_EXT_USE => true, -- implement external memory bus interface?
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MEM_DSPACE_BASE => x"80000000", -- base address of data memory space
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MEM_EXT_REG_STAGES => 2, -- number of interface register stages (0,1,2)
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MEM_DSPACE_SIZE => 8*1024, -- total size of data memory space in byte
|
MEM_EXT_TIMEOUT => 15, -- cycles after which a valid bus access will timeout
|
MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
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-- Processor peripherals --
|
MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
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IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
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-- Memory configuration: External memory interface --
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IO_MTIME_USE => true, -- implement machine system timer (MTIME)?
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MEM_EXT_USE => true, -- implement external memory bus interface?
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IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
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MEM_EXT_REG_STAGES => 2, -- number of interface register stages (0,1,2)
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IO_SPI_USE => true, -- implement serial peripheral interface (SPI)?
|
MEM_EXT_TIMEOUT => 15, -- cycles after which a valid bus access will timeout
|
IO_TWI_USE => true, -- implement two-wire interface (TWI)?
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-- Processor peripherals --
|
IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)?
|
IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
|
IO_WDT_USE => true, -- implement watch dog timer (WDT)?
|
IO_MTIME_USE => true, -- implement machine system timer (MTIME)?
|
IO_CLIC_USE => true, -- implement core local interrupt controller (CLIC)?
|
IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_TRNG_USE => false, -- implement true random number generator (TRNG)?
|
IO_SPI_USE => true, -- implement serial peripheral interface (SPI)?
|
IO_DEVNULL_USE => true -- implement dummy device (DEVNULL)?
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IO_TWI_USE => true, -- implement two-wire interface (TWI)?
|
)
|
IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)?
|
port map (
|
IO_WDT_USE => true, -- implement watch dog timer (WDT)?
|
-- Global control --
|
IO_CLIC_USE => true, -- implement core local interrupt controller (CLIC)?
|
clk_i => clk_gen, -- global clock, rising edge
|
IO_TRNG_USE => false -- implement true random number generator (TRNG)?
|
rstn_i => rst_gen, -- global reset, low-active, async
|
)
|
-- Wishbone bus interface --
|
port map (
|
wb_adr_o => wb_cpu.addr, -- address
|
-- Global control --
|
wb_dat_i => wb_cpu.rdata, -- read data
|
clk_i => clk_gen, -- global clock, rising edge
|
wb_dat_o => wb_cpu.wdata, -- write data
|
rstn_i => rst_gen, -- global reset, low-active, async
|
wb_we_o => wb_cpu.we, -- read/write
|
-- Wishbone bus interface --
|
wb_sel_o => wb_cpu.sel, -- byte enable
|
wb_adr_o => wb_cpu.addr, -- address
|
wb_stb_o => wb_cpu.stb, -- strobe
|
wb_dat_i => wb_cpu.rdata, -- read data
|
wb_cyc_o => wb_cpu.cyc, -- valid cycle
|
wb_dat_o => wb_cpu.wdata, -- write data
|
wb_ack_i => wb_cpu.ack, -- transfer acknowledge
|
wb_we_o => wb_cpu.we, -- read/write
|
wb_err_i => wb_cpu.err, -- transfer error
|
wb_sel_o => wb_cpu.sel, -- byte enable
|
-- GPIO --
|
wb_stb_o => wb_cpu.stb, -- strobe
|
gpio_o => gpio, -- parallel output
|
wb_cyc_o => wb_cpu.cyc, -- valid cycle
|
gpio_i => gpio, -- parallel input
|
wb_ack_i => wb_cpu.ack, -- transfer acknowledge
|
-- UART --
|
wb_err_i => wb_cpu.err, -- transfer error
|
uart_txd_o => uart_txd, -- UART send data
|
-- GPIO --
|
uart_rxd_i => uart_txd, -- UART receive data
|
gpio_o => gpio, -- parallel output
|
-- SPI --
|
gpio_i => gpio, -- parallel input
|
spi_sclk_o => open, -- serial clock line
|
-- UART --
|
spi_mosi_o => spi_data, -- serial data line out
|
uart_txd_o => uart_txd, -- UART send data
|
spi_miso_i => spi_data, -- serial data line in
|
uart_rxd_i => uart_txd, -- UART receive data
|
spi_csn_o => open, -- SPI CS
|
-- SPI --
|
-- TWI --
|
spi_sclk_o => open, -- serial clock line
|
twi_sda_io => twi_sda, -- twi serial data line
|
spi_mosi_o => spi_data, -- serial data line out
|
twi_scl_io => twi_scl, -- twi serial clock line
|
spi_miso_i => spi_data, -- serial data line in
|
-- PWM --
|
spi_csn_o => open, -- SPI CS
|
pwm_o => open, -- pwm channels
|
-- TWI --
|
-- Interrupts --
|
twi_sda_io => twi_sda, -- twi serial data line
|
ext_irq_i => (others => '0'), -- external interrupt request
|
twi_scl_io => twi_scl, -- twi serial clock line
|
ext_ack_o => open -- external interrupt request acknowledge
|
-- PWM --
|
);
|
pwm_o => open, -- pwm channels
|
|
-- Interrupts --
|
-- TWI termination --
|
ext_irq_i => (others => '0'), -- external interrupt request
|
twi_scl <= 'H';
|
ext_ack_o => open -- external interrupt request acknowledge
|
twi_sda <= 'H';
|
);
|
|
|
-- Wishbone read-back --
|
-- twi termination --
|
wb_cpu.rdata <= wb_mem_rdata;
|
twi_scl <= 'H';
|
wb_cpu.ack <= wb_mem_ack;
|
twi_sda <= 'H';
|
wb_cpu.err <= '0';
|
|
|
|
|
-- Console UART Receiver ------------------------------------------------------------------
|
-- Console UART Receiver ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
uart_rx_console: process(clk_gen)
|
uart_rx_console: process(clk_gen)
|
variable i, j : integer;
|
variable i : integer;
|
variable line_tmp : line;
|
variable l : line;
|
begin
|
begin
|
|
-- "UART" --
|
-- "UART" --
|
if rising_edge(clk_gen) then
|
if rising_edge(clk_gen) then
|
-- synchronizer --
|
-- synchronizer --
|
uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
|
uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
|
-- arbiter --
|
-- arbiter --
|
if (uart_rx_busy = '0') then -- idle
|
if (uart_rx_busy = '0') then -- idle
|
uart_rx_busy <= '0';
|
uart_rx_busy <= '0';
|
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
|
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
|
uart_rx_bitcnt <= 9;
|
uart_rx_bitcnt <= 9;
|
if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
|
if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
|
uart_rx_busy <= '1';
|
uart_rx_busy <= '1';
|
end if;
|
end if;
|
else
|
else
|
if (uart_rx_baud_cnt = 0.0) then
|
if (uart_rx_baud_cnt = 0.0) then
|
if (uart_rx_bitcnt = 1) then
|
-- adapt to the inter-frame pause - which is not implemented in the neo430 uart ;)
|
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
|
if (uart_rx_bitcnt = 1) then
|
else
|
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
|
uart_rx_baud_cnt <= round(baud_val_c);
|
else
|
end if;
|
uart_rx_baud_cnt <= round(baud_val_c);
|
if (uart_rx_bitcnt = 0) then
|
end if;
|
uart_rx_busy <= '0'; -- done
|
if (uart_rx_bitcnt = 0) then
|
i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));
|
uart_rx_busy <= '0'; -- done
|
|
i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));
|
if (i < 32) or (i > 32+95) then -- printable char?
|
j := i - 32;
|
report "SIM_UART TX: (" & integer'image(i) & ")"; -- print code
|
if (j < 0) or (j > 95) then
|
else
|
j := 0; -- undefined = SPACE
|
report "SIM_UART TX: " & character'val(i); -- print ASCII
|
end if;
|
end if;
|
|
|
if (i < 32) or (j > 32+95) then
|
if (i = 10) then -- Linux line break
|
report "UART TX: (" & integer'image(i) & ")"; -- print code
|
writeline(file_uart_tx_out, l);
|
else
|
elsif (i /= 13) then -- Remove additional carriage return
|
report "UART TX: " & ascii_lut(j); -- print ASCII
|
write(l, character'val(i));
|
end if;
|
end if;
|
|
else
|
if (i = 10) then -- Linux line break
|
uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
|
writeline(file_uart_tx_out, line_tmp);
|
uart_rx_bitcnt <= uart_rx_bitcnt - 1;
|
elsif (i /= 13) then -- Remove additional carriage return
|
end if;
|
write(line_tmp, ascii_lut(j));
|
else
|
end if;
|
uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
|
else
|
end if;
|
uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
|
end if;
|
uart_rx_bitcnt <= uart_rx_bitcnt - 1;
|
end if;
|
end if;
|
end process uart_rx_console;
|
else
|
|
uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
|
|
end if;
|
-- Wishbone Memory ------------------------------------------------------------------------
|
end if;
|
-- -------------------------------------------------------------------------------------------
|
end if;
|
wb_mem_file_access: process(clk_gen)
|
end process uart_rx_console;
|
begin
|
|
if rising_edge(clk_gen) then
|
|
rb_en <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en and (not wb_cpu.we); -- read-back control
|
-- Wishbone Memory ------------------------------------------------------------------------
|
wb_mem_ack <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en; -- wishbone acknowledge
|
-- -------------------------------------------------------------------------------------------
|
if ((wb_cpu.cyc and wb_cpu.stb and wb_acc_en and wb_cpu.we) = '1') then -- valid write access
|
wb_mem_file_access: process(clk_gen)
|
for i in 0 to 3 loop
|
begin
|
if (wb_cpu.sel(i) = '1') then
|
if rising_edge(clk_gen) then
|
wb_mem_file(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_cpu.wdata(7+i*8 downto 0+i*8);
|
rb_en <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en and (not wb_cpu.we); -- read-back control
|
end if;
|
wb_cpu.ack <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en; -- wishbone acknowledge
|
end loop; -- i
|
if ((wb_cpu.cyc and wb_cpu.stb and wb_acc_en and wb_cpu.we) = '1') then -- valid write access
|
end if;
|
for i in 0 to 3 loop
|
r_data <= wb_mem_file(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned
|
if (wb_cpu.sel(i) = '1') then
|
end if;
|
wb_mem_file(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_cpu.wdata(7+i*8 downto 0+i*8);
|
end process wb_mem_file_access;
|
end if;
|
|
end loop; -- i
|
-- wb mem access --
|
end if;
|
wb_acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0';
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r_data <= wb_mem_file(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned
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end if;
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-- output gate --
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end process wb_mem_file_access;
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wb_mem_rdata <= r_data when (rb_en = '1') else (others=> '0');
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-- wb mem access --
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wb_acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0';
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end neorv32_tb_rtl;
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-- output gate --
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wb_cpu.rdata <= r_data when (rb_en = '1') else (others=> '0');
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wb_cpu.err <= '0';
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end neorv32_tb_rtl;
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