| Line 179... |
Line 179... |
-- Internal Data memory --
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-- Internal Data memory --
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MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
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MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
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-- External memory interface --
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-- External memory interface --
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MEM_EXT_USE => true, -- implement external memory bus interface?
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MEM_EXT_USE => true, -- implement external memory bus interface?
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MEM_EXT_REG_STAGES => 2, -- number of interface register stages (0,1,2)
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
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IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_USE => true, -- implement machine system timer (MTIME)?
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IO_MTIME_USE => true, -- implement machine system timer (MTIME)?
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IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
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IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
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IO_SPI_USE => true, -- implement serial peripheral interface (SPI)?
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IO_SPI_USE => true, -- implement serial peripheral interface (SPI)?
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| Line 310... |
Line 309... |
wb_mem.rdata(0) <= wb_ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned
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wb_mem.rdata(0) <= wb_ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned
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-- virtual read and ack latency --
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-- virtual read and ack latency --
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if (wb_mem_latency_c > 1) then
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if (wb_mem_latency_c > 1) then
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for i in 1 to wb_mem_latency_c-1 loop
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for i in 1 to wb_mem_latency_c-1 loop
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wb_mem.rdata(i) <= wb_mem.rdata(i-1);
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wb_mem.rdata(i) <= wb_mem.rdata(i-1);
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wb_mem.rb_en(i) <= wb_mem.rb_en(i-1);
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wb_mem.rb_en(i) <= wb_mem.rb_en(i-1) and wb_cpu.cyc;
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wb_mem.ack(i) <= wb_mem.ack(i-1) and wb_cpu.cyc;
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wb_mem.ack(i) <= wb_mem.ack(i-1) and wb_cpu.cyc;
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end loop;
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end loop;
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end if;
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end if;
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end if;
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end if;
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end process wb_mem_ram_access;
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end process wb_mem_ram_access;
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| Line 322... |
Line 321... |
-- wishbone memory access? --
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-- wishbone memory access? --
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wb_mem.acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0';
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wb_mem.acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0';
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|
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-- output to cpu --
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-- output to cpu --
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wb_cpu.rdata <= wb_mem.rdata(wb_mem_latency_c-1) when (wb_mem.rb_en(wb_mem_latency_c-1) = '1') else (others=> '0'); -- data output gate
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wb_cpu.rdata <= wb_mem.rdata(wb_mem_latency_c-1) when (wb_mem.rb_en(wb_mem_latency_c-1) = '1') else (others=> '0'); -- data output gate
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wb_cpu.ack <= wb_mem.ack(wb_mem_latency_c-1) and wb_cpu.cyc; -- another AND for classic/standard wishbone transactions
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wb_cpu.ack <= wb_mem.ack(wb_mem_latency_c-1);
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wb_cpu.err <= '0';
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wb_cpu.err <= '0';
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|
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end neorv32_tb_rtl;
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end neorv32_tb_rtl;
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