| Line 1... |
Line 1... |
-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Default Testbench >> #
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-- # << NEORV32 - Default Testbench >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # This testbench provides a virtual UART receiver connected to the processor's uart_txd_o #
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-- # This testbench provides a virtual UART receiver connected to the processor's uart_txd_o #
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-- # signal. The received chars are shown in the simulator console and also written to a file #
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-- # signal. The received chars are shown in the simulator console and also written to a file #
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-- # ("neorv32.testbench_uart.out"). Futhermore, this testbench provides a simple RAM connected #
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-- # ("neorv32.testbench_uart.out"). #
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-- # to the external Wishbone bus. The testbench configures the processor with all optional #
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-- # #
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-- # elements enabled by default. #
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-- # Furthermore, this testbench provides two external memories (ext_mem_a and ext_mem_b) coupled #
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-- # via Wishbone. ext_mem_a is initialized with the application_init_image and can be used as #
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-- # external boot memory (external IMEM). #
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-- # ext_mem_b is a small uninitialized memory that can be uased as external memory-mapped IO. #
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-- # #
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-- # Use the "User Configuration" section to configure the testbench according to your need. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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Line 58... |
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architecture neorv32_tb_rtl of neorv32_tb is
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architecture neorv32_tb_rtl of neorv32_tb is
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-- User Configuration ---------------------------------------------------------------------
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-- User Configuration ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant t_clock_c : time := 10 ns; -- main clock period
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-- general --
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constant f_clock_c : real := 100000000.0; -- main clock in Hz
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constant boot_external_c : boolean := false; -- false: boot from proc-internal IMEM, true: boot from (initialized) simulated ext. mem A
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constant f_clock_nat_c : natural := 100000000; -- main clock in Hz
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constant imem_size_c : natural := 16*1024; -- size in bytes of processor-internal IMEM / external mem A
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constant baud_rate_c : real := 19200.0; -- standard UART baudrate
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constant f_clock_c : natural := 100000000; -- main clock in Hz
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--
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-- UART --
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constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address
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constant baud_rate_c : natural := 19200; -- standard UART baudrate
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constant wb_mem_size_c : natural := 256; -- wishbone memory size in bytes
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-- simulated external Wishbone memory A (can be used as external IMEM) --
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constant wb_mem_latency_c : natural := 8; -- latency in clock cycles (min 1)
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constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (IMEM base)
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constant ext_mem_a_size_c : natural := imem_size_c; -- wishbone memory size in bytes
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constant ext_mem_a_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay
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-- simulated external Wishbone memory B (can be used as external IO) --
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constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
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constant ext_mem_b_size_c : natural := 64; -- wishbone memory size in bytes
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constant ext_mem_b_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- internals - hands off! --
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constant boot_imem_c : boolean := not boot_external_c;
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-- text.io --
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-- text.io --
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file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
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file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
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-- internal configuration --
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-- internal configuration --
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constant baud_val_c : real := f_clock_c / baud_rate_c;
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constant baud_val_c : real := real(f_clock_c) / real(baud_rate_c);
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constant f_clk_c : natural := natural(f_clock_c);
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constant t_clock_c : time := (1 sec) / f_clock_c;
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-- generators --
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-- generators --
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signal clk_gen, rst_gen : std_ulogic := '0';
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signal clk_gen, rst_gen : std_ulogic := '0';
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-- simulation uart receiver --
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-- simulation uart receiver --
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| Line 103... |
Line 117... |
cyc : std_ulogic; -- valid cycle
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cyc : std_ulogic; -- valid cycle
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ack : std_ulogic; -- transfer acknowledge
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ack : std_ulogic; -- transfer acknowledge
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err : std_ulogic; -- transfer error
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err : std_ulogic; -- transfer error
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tag : std_ulogic_vector(2 downto 0); -- tag
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tag : std_ulogic_vector(2 downto 0); -- tag
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end record;
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end record;
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signal wb_cpu : wishbone_t;
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signal wb_cpu, wb_mem_a, wb_mem_b : wishbone_t;
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-- Wishbone memory --
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-- Wishbone memories --
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type wb_mem_ram_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type wb_mem_read_latency_t is array (0 to wb_mem_latency_c-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0);
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-- init function --
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-- init function --
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-- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
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-- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
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impure function init_wbmem(init : application_init_image_t) return wb_mem_ram_t is
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impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
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variable mem_v : wb_mem_ram_t;
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variable mem_v : ext_mem_a_ram_t;
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begin
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begin
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mem_v := (others => (others => '0'));
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mem_v := (others => (others => '0'));
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for i in 0 to init'length-1 loop -- init only in range of source data array
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for i in 0 to init'length-1 loop -- init only in range of source data array
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mem_v(i) := init(i);
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mem_v(i) := init(i);
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end loop; -- i
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end loop; -- i
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return mem_v;
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return mem_v;
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end function init_wbmem;
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end function init_wbmem;
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-- ---------------------------------------------- --
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-- external memory components --
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-- How to simulate a boot from an external memory --
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signal ext_ram_a : ext_mem_a_ram_t := init_wbmem(application_init_image); -- initialized, used to simulate external instruction boot memory
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-- ---------------------------------------------- --
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signal ext_ram_b : ext_mem_b_ram_t; -- uninitialized, used to simulate external IO
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-- The simulated Wishbone memory can be initialized with the compiled application init.
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-- 1. Uncomment the init_wbmem function below; this will initialize the simulated wishbone memory with the neorv32_application_image.vhd image
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-- 2. Increase the wb_mem_size_c constant above to (at least) the size of the application image (like 16kB -> 16*1024)
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-- 3. Disable the processor-internal IMEM in the processor instantiation below (MEM_INT_IMEM_USE => false)
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-- 4. Set the Wishbone memory base address wb_mem_base_addr_c (above) to zero (constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000";)
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-- 5. Simulate!
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signal wb_ram : wb_mem_ram_t;-- := init_wbmem(application_init_image); -- uncomment if you want to init the WB ram with app image
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type ext_mem_t is record
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rdata : ext_mem_read_latency_t;
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type wb_mem_t is record
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rdata : wb_mem_read_latency_t;
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acc_en : std_ulogic;
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acc_en : std_ulogic;
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ack : std_ulogic_vector(wb_mem_latency_c-1 downto 0);
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ack : std_ulogic_vector(ext_mem_a_latency_c-1 downto 0);
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rb_en : std_ulogic_vector(wb_mem_latency_c-1 downto 0);
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end record;
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end record;
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signal wb_mem : wb_mem_t;
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signal ext_mem_a, ext_mem_b : ext_mem_t;
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begin
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begin
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-- Clock/Reset Generator ------------------------------------------------------------------
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-- Clock/Reset Generator ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 154... |
Line 160... |
-- CPU Core -------------------------------------------------------------------------------
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-- CPU Core -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_top_inst: neorv32_top
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neorv32_top_inst: neorv32_top
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generic map (
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generic map (
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-- General --
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-- General --
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CLOCK_FREQUENCY => f_clock_nat_c, -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
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BOOTLOADER_USE => false, -- implement processor-internal bootloader?
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BOOTLOADER_USE => false, -- implement processor-internal bootloader?
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USER_CODE => x"12345678", -- custom user code
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USER_CODE => x"12345678", -- custom user code
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HW_THREAD_ID => x"00000000", -- hardware thread id (hartid)
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HW_THREAD_ID => x"00000000", -- hardware thread id (hartid)
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
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| Line 173... |
Line 179... |
-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_USE => true, -- implement PMP?
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PMP_USE => true, -- implement PMP?
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PMP_NUM_REGIONS => 4, -- number of regions (max 16)
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PMP_NUM_REGIONS => 4, -- number of regions (max 16)
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PMP_GRANULARITY => 14, -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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PMP_GRANULARITY => 14, -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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-- Internal Instruction memory --
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-- Internal Instruction memory --
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MEM_INT_IMEM_USE => true, -- implement processor-internal instruction memory
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MEM_INT_IMEM_USE => boot_imem_c, -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE => imem_size_c, -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
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MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
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-- Internal Data memory --
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-- Internal Data memory --
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MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
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MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
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-- External memory interface --
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-- External memory interface --
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| Line 257... |
Line 263... |
uart_rx_bitcnt <= 9;
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uart_rx_bitcnt <= 9;
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if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
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if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
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uart_rx_busy <= '1';
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uart_rx_busy <= '1';
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end if;
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end if;
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else
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else
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if (uart_rx_baud_cnt = 0.0) then
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if (uart_rx_baud_cnt <= 0.0) then
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if (uart_rx_bitcnt = 1) then
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if (uart_rx_bitcnt = 1) then
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uart_rx_baud_cnt <= round(0.5 * baud_val_c);
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uart_rx_baud_cnt <= round(0.5 * baud_val_c);
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else
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else
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uart_rx_baud_cnt <= round(baud_val_c);
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uart_rx_baud_cnt <= round(baud_val_c);
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end if;
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end if;
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| Line 290... |
Line 296... |
end if;
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end if;
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end if;
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end if;
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end process uart_rx_console;
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end process uart_rx_console;
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-- Wishbone Memory (simulated external memory) --------------------------------------------
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-- Wishbone Fabric ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- CPU broadcast signals --
|
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wb_mem_a.addr <= wb_cpu.addr;
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wb_mem_b.addr <= wb_cpu.addr;
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wb_mem_a.wdata <= wb_cpu.wdata;
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wb_mem_b.wdata <= wb_cpu.wdata;
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wb_mem_a.we <= wb_cpu.we;
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wb_mem_b.we <= wb_cpu.we;
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wb_mem_a.sel <= wb_cpu.sel;
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wb_mem_b.sel <= wb_cpu.sel;
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wb_mem_a.tag <= wb_cpu.tag;
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wb_mem_b.tag <= wb_cpu.tag;
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wb_mem_a.cyc <= wb_cpu.cyc;
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wb_mem_b.cyc <= wb_cpu.cyc;
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-- CPU read-back signals (no mux here since peripherals have "output gates") --
|
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wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata;
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wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack;
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wb_cpu.err <= wb_mem_a.err or wb_mem_b.err;
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|
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-- peripheral select via STROBE signal --
|
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wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
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wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
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-- Wishbone Memory A (simulated external memory) ------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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wb_mem_ram_access: process(clk_gen)
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ext_mem_a_access: process(clk_gen)
|
begin
|
begin
|
if rising_edge(clk_gen) then
|
if rising_edge(clk_gen) then
|
-- control --
|
-- control --
|
wb_mem.rb_en(0) <= wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en and (not wb_cpu.we); -- read-back control
|
ext_mem_a.ack(0) <= wb_mem_a.cyc and wb_mem_a.stb; -- wishbone acknowledge
|
wb_mem.ack(0) <= wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en; -- wishbone acknowledge
|
|
-- write access --
|
-- write access --
|
if ((wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en and wb_cpu.we) = '1') then -- valid write access
|
if ((wb_mem_a.cyc and wb_mem_a.stb and wb_mem_a.we) = '1') then -- valid write access
|
for i in 0 to 3 loop
|
for i in 0 to 3 loop
|
if (wb_cpu.sel(i) = '1') then
|
if (wb_mem_a.sel(i) = '1') then
|
wb_ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_cpu.wdata(7+i*8 downto 0+i*8);
|
ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_a.wdata(7+i*8 downto 0+i*8);
|
end if;
|
end if;
|
end loop; -- i
|
end loop; -- i
|
end if;
|
end if;
|
|
|
-- read access --
|
-- read access --
|
wb_mem.rdata(0) <= wb_ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned
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ext_mem_a.rdata(0) <= ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2)))); -- word aligned
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-- virtual read and ack latency --
|
-- virtual read and ack latency --
|
if (wb_mem_latency_c > 1) then
|
if (ext_mem_a_latency_c > 1) then
|
for i in 1 to wb_mem_latency_c-1 loop
|
for i in 1 to ext_mem_a_latency_c-1 loop
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wb_mem.rdata(i) <= wb_mem.rdata(i-1);
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ext_mem_a.rdata(i) <= ext_mem_a.rdata(i-1);
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wb_mem.rb_en(i) <= wb_mem.rb_en(i-1) and wb_cpu.cyc;
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ext_mem_a.ack(i) <= ext_mem_a.ack(i-1) and wb_mem_a.cyc;
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wb_mem.ack(i) <= wb_mem.ack(i-1) and wb_cpu.cyc;
|
|
end loop;
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end loop;
|
end if;
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end if;
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|
|
|
-- bus output register --
|
|
wb_mem_a.err <= '0';
|
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if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
|
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wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
|
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wb_mem_a.ack <= '1';
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else
|
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wb_mem_a.rdata <= (others => '0');
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wb_mem_a.ack <= '0';
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|
end if;
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end if;
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end process ext_mem_a_access;
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|
|
-- Wishbone Memory B (simulated external memory) ------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
ext_mem_b_access: process(clk_gen)
|
|
begin
|
|
if rising_edge(clk_gen) then
|
|
-- control --
|
|
ext_mem_b.ack(0) <= wb_mem_b.cyc and wb_mem_b.stb; -- wishbone acknowledge
|
|
|
|
-- write access --
|
|
if ((wb_mem_b.cyc and wb_mem_b.stb and wb_mem_b.we) = '1') then -- valid write access
|
|
for i in 0 to 3 loop
|
|
if (wb_mem_b.sel(i) = '1') then
|
|
ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_b.wdata(7+i*8 downto 0+i*8);
|
|
end if;
|
|
end loop; -- i
|
end if;
|
end if;
|
end process wb_mem_ram_access;
|
|
|
|
-- wishbone memory access? --
|
-- read access --
|
wb_mem.acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0';
|
ext_mem_b.rdata(0) <= ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2)))); -- word aligned
|
|
-- virtual read and ack latency --
|
|
if (ext_mem_b_latency_c > 1) then
|
|
for i in 1 to ext_mem_b_latency_c-1 loop
|
|
ext_mem_b.rdata(i) <= ext_mem_b.rdata(i-1);
|
|
ext_mem_b.ack(i) <= ext_mem_b.ack(i-1) and wb_mem_b.cyc;
|
|
end loop;
|
|
end if;
|
|
|
-- output to cpu --
|
-- bus output register --
|
wb_cpu.rdata <= wb_mem.rdata(wb_mem_latency_c-1) when (wb_mem.rb_en(wb_mem_latency_c-1) = '1') else (others=> '0'); -- data output gate
|
wb_mem_b.err <= '0';
|
wb_cpu.ack <= wb_mem.ack(wb_mem_latency_c-1);
|
if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
|
wb_cpu.err <= '0';
|
wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
|
|
wb_mem_b.ack <= '1';
|
|
else
|
|
wb_mem_b.rdata <= (others => '0');
|
|
wb_mem_b.ack <= '0';
|
|
end if;
|
|
end if;
|
|
end process ext_mem_b_access;
|
|
|
|
|
end neorv32_tb_rtl;
|
end neorv32_tb_rtl;
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No newline at end of file
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No newline at end of file
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