| Line 59... |
Line 59... |
architecture neorv32_tb_rtl of neorv32_tb is
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architecture neorv32_tb_rtl of neorv32_tb is
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-- User Configuration ---------------------------------------------------------------------
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-- User Configuration ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- general --
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-- general --
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constant boot_external_c : boolean := false; -- false: boot from proc-internal IMEM, true: boot from (initialized) simulated ext. mem A
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constant ext_imem_c : boolean := false; -- false: use and boot from proc-internal IMEM, true: use and boot from external (initialized) simulated IMEM (ext. mem A)
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constant ext_dmem_c : boolean := false; -- false: use proc-internal DMEM, true: use external simulated DMEM (ext. mem B)
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constant imem_size_c : natural := 16*1024; -- size in bytes of processor-internal IMEM / external mem A
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constant imem_size_c : natural := 16*1024; -- size in bytes of processor-internal IMEM / external mem A
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constant dmem_size_c : natural := 8*1024; -- size in bytes of processor-internal DMEM / external mem B
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constant f_clock_c : natural := 100000000; -- main clock in Hz
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constant f_clock_c : natural := 100000000; -- main clock in Hz
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-- UART --
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constant baud_rate_c : natural := 19200; -- simulation UART output baudrate
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constant baud_rate_c : natural := 19200; -- standard UART baudrate
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-- simulated external Wishbone memory A (can be used as external IMEM) --
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-- simulated external Wishbone memory A (can be used as external IMEM) --
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constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (IMEM base)
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constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base)
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constant ext_mem_a_size_c : natural := imem_size_c; -- wishbone memory size in bytes
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constant ext_mem_a_size_c : natural := imem_size_c; -- wishbone memory size in bytes
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constant ext_mem_a_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay
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constant ext_mem_a_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay
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-- simulated external Wishbone memory B (can be used as external IO) --
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-- simulated external Wishbone memory B (can be used as external DMEM) --
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constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
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constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- wishbone memory base address (external DMEM base)
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constant ext_mem_b_size_c : natural := 64; -- wishbone memory size in bytes
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constant ext_mem_b_size_c : natural := dmem_size_c; -- wishbone memory size in bytes
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constant ext_mem_b_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay
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constant ext_mem_b_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay
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-- simulated external Wishbone memory C (can be used as external IO) --
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constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
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constant ext_mem_c_size_c : natural := 64; -- wishbone memory size in bytes
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constant ext_mem_c_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- internals - hands off! --
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-- internals - hands off! --
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constant boot_imem_c : boolean := not boot_external_c;
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constant int_imem_c : boolean := not ext_imem_c;
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constant int_dmem_c : boolean := not ext_dmem_c;
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constant baud_val_c : real := real(f_clock_c) / real(baud_rate_c);
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constant t_clock_c : time := (1 sec) / f_clock_c;
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-- text.io --
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-- text.io --
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file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
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file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
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-- internal configuration --
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constant baud_val_c : real := real(f_clock_c) / real(baud_rate_c);
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constant t_clock_c : time := (1 sec) / f_clock_c;
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-- generators --
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-- generators --
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signal clk_gen, rst_gen : std_ulogic := '0';
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signal clk_gen, rst_gen : std_ulogic := '0';
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-- simulation uart receiver --
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-- simulation uart receiver --
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signal uart_txd : std_ulogic;
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signal uart_txd : std_ulogic;
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| Line 116... |
Line 120... |
stb : std_ulogic; -- strobe
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stb : std_ulogic; -- strobe
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cyc : std_ulogic; -- valid cycle
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cyc : std_ulogic; -- valid cycle
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ack : std_ulogic; -- transfer acknowledge
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ack : std_ulogic; -- transfer acknowledge
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err : std_ulogic; -- transfer error
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err : std_ulogic; -- transfer error
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tag : std_ulogic_vector(2 downto 0); -- tag
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tag : std_ulogic_vector(2 downto 0); -- tag
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lock : std_ulogic; -- locked/exclusive bus access
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end record;
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end record;
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signal wb_cpu, wb_mem_a, wb_mem_b : wishbone_t;
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signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c : wishbone_t;
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-- Wishbone memories --
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-- Wishbone memories --
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type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0);
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type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0);
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-- init function --
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-- init function --
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-- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
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-- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
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impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
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impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
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| Line 137... |
Line 143... |
end loop; -- i
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end loop; -- i
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return mem_v;
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return mem_v;
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end function init_wbmem;
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end function init_wbmem;
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-- external memory components --
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-- external memory components --
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signal ext_ram_a : ext_mem_a_ram_t := init_wbmem(application_init_image); -- initialized, used to simulate external instruction boot memory
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signal ext_ram_a : ext_mem_a_ram_t := init_wbmem(application_init_image); -- initialized, used to simulate external IMEM
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signal ext_ram_b : ext_mem_b_ram_t; -- uninitialized, used to simulate external IO
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signal ext_ram_b : ext_mem_b_ram_t := (others => (others => '0')); -- zero, used to simulate external DMEM
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signal ext_ram_c : ext_mem_c_ram_t; -- uninitialized, used to simulate external IO
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type ext_mem_t is record
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type ext_mem_t is record
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rdata : ext_mem_read_latency_t;
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rdata : ext_mem_read_latency_t;
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acc_en : std_ulogic;
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acc_en : std_ulogic;
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ack : std_ulogic_vector(ext_mem_a_latency_c-1 downto 0);
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ack : std_ulogic_vector(ext_mem_a_latency_c-1 downto 0);
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end record;
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end record;
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signal ext_mem_a, ext_mem_b : ext_mem_t;
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signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t;
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begin
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begin
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-- Clock/Reset Generator ------------------------------------------------------------------
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-- Clock/Reset Generator ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 165... |
Line 172... |
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
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BOOTLOADER_USE => false, -- implement processor-internal bootloader?
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BOOTLOADER_USE => false, -- implement processor-internal bootloader?
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USER_CODE => x"12345678", -- custom user code
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USER_CODE => x"12345678", -- custom user code
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HW_THREAD_ID => x"00000000", -- hardware thread id (hartid)
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HW_THREAD_ID => x"00000000", -- hardware thread id (hartid)
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A => true, -- implement atomic extension?
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
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CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
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CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
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| Line 179... |
Line 187... |
-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_USE => true, -- implement PMP?
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PMP_USE => true, -- implement PMP?
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PMP_NUM_REGIONS => 4, -- number of regions (max 16)
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PMP_NUM_REGIONS => 4, -- number of regions (max 16)
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PMP_GRANULARITY => 14, -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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PMP_GRANULARITY => 14, -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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-- Internal Instruction memory --
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-- Internal Instruction memory --
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MEM_INT_IMEM_USE => boot_imem_c, -- implement processor-internal instruction memory
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MEM_INT_IMEM_USE => int_imem_c , -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE => imem_size_c, -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE => imem_size_c, -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
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MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
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-- Internal Data memory --
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-- Internal Data memory --
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MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
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MEM_INT_DMEM_USE => int_dmem_c, -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE => dmem_size_c, -- size of processor-internal data memory in bytes
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-- External memory interface --
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-- External memory interface --
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MEM_EXT_USE => true, -- implement external memory bus interface?
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MEM_EXT_USE => true, -- implement external memory bus interface?
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
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IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_USE => true, -- implement machine system timer (MTIME)?
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IO_MTIME_USE => true, -- implement machine system timer (MTIME)?
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IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
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IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
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IO_SPI_USE => true, -- implement serial peripheral interface (SPI)?
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IO_SPI_USE => true, -- implement serial peripheral interface (SPI)?
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IO_TWI_USE => true, -- implement two-wire interface (TWI)?
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IO_TWI_USE => true, -- implement two-wire interface (TWI)?
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IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)?
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IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE => true, -- implement watch dog timer (WDT)?
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IO_WDT_USE => true, -- implement watch dog timer (WDT)?
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IO_TRNG_USE => false, -- DEFAULT TRNG CONFIG CANNOT BE SIMULATED!
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IO_TRNG_USE => false, -- trng cannot be simulated
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IO_CFU0_USE => true, -- implement custom functions unit 0 (CFU0)?
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IO_CFU0_USE => true, -- implement custom functions unit 0 (CFU0)?
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IO_CFU1_USE => true -- implement custom functions unit 1 (CFU1)?
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IO_CFU1_USE => true -- implement custom functions unit 1 (CFU1)?
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)
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)
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port map (
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port map (
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-- Global control --
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-- Global control --
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| Line 212... |
Line 220... |
wb_dat_o => wb_cpu.wdata, -- write data
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wb_dat_o => wb_cpu.wdata, -- write data
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wb_we_o => wb_cpu.we, -- read/write
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wb_we_o => wb_cpu.we, -- read/write
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wb_sel_o => wb_cpu.sel, -- byte enable
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wb_sel_o => wb_cpu.sel, -- byte enable
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wb_stb_o => wb_cpu.stb, -- strobe
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wb_stb_o => wb_cpu.stb, -- strobe
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wb_cyc_o => wb_cpu.cyc, -- valid cycle
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wb_cyc_o => wb_cpu.cyc, -- valid cycle
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wb_lock_o => wb_cpu.lock, -- locked/exclusive bus access
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wb_ack_i => wb_cpu.ack, -- transfer acknowledge
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wb_ack_i => wb_cpu.ack, -- transfer acknowledge
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wb_err_i => wb_cpu.err, -- transfer error
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wb_err_i => wb_cpu.err, -- transfer error
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-- Advanced memory control signals --
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-- Advanced memory control signals --
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fence_o => open, -- indicates an executed FENCE operation
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fence_o => open, -- indicates an executed FENCE operation
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fencei_o => open, -- indicates an executed FENCEI operation
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fencei_o => open, -- indicates an executed FENCEI operation
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| Line 300... |
Line 309... |
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-- Wishbone Fabric ------------------------------------------------------------------------
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-- Wishbone Fabric ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- CPU broadcast signals --
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-- CPU broadcast signals --
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wb_mem_a.addr <= wb_cpu.addr;
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wb_mem_a.addr <= wb_cpu.addr;
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wb_mem_b.addr <= wb_cpu.addr;
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wb_mem_a.wdata <= wb_cpu.wdata;
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wb_mem_a.wdata <= wb_cpu.wdata;
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wb_mem_b.wdata <= wb_cpu.wdata;
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wb_mem_a.we <= wb_cpu.we;
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wb_mem_a.we <= wb_cpu.we;
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wb_mem_b.we <= wb_cpu.we;
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wb_mem_a.sel <= wb_cpu.sel;
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wb_mem_a.sel <= wb_cpu.sel;
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wb_mem_b.sel <= wb_cpu.sel;
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wb_mem_a.tag <= wb_cpu.tag;
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wb_mem_a.tag <= wb_cpu.tag;
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wb_mem_b.tag <= wb_cpu.tag;
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wb_mem_a.cyc <= wb_cpu.cyc;
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wb_mem_a.cyc <= wb_cpu.cyc;
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wb_mem_a.lock <= wb_cpu.lock;
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wb_mem_b.addr <= wb_cpu.addr;
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wb_mem_b.wdata <= wb_cpu.wdata;
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wb_mem_b.we <= wb_cpu.we;
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wb_mem_b.sel <= wb_cpu.sel;
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wb_mem_b.tag <= wb_cpu.tag;
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wb_mem_b.cyc <= wb_cpu.cyc;
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wb_mem_b.cyc <= wb_cpu.cyc;
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wb_mem_b.lock <= wb_cpu.lock;
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wb_mem_c.addr <= wb_cpu.addr;
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wb_mem_c.wdata <= wb_cpu.wdata;
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wb_mem_c.we <= wb_cpu.we;
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wb_mem_c.sel <= wb_cpu.sel;
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wb_mem_c.tag <= wb_cpu.tag;
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wb_mem_c.cyc <= wb_cpu.cyc;
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wb_mem_c.lock <= wb_cpu.lock;
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-- CPU read-back signals (no mux here since peripherals have "output gates") --
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-- CPU read-back signals (no mux here since peripherals have "output gates") --
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wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata;
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wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata;
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wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack;
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wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack;
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wb_cpu.err <= wb_mem_a.err or wb_mem_b.err;
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wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err;
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-- peripheral select via STROBE signal --
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-- peripheral select via STROBE signal --
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wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
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wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
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wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
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wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
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wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
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-- Wishbone Memory A (simulated external memory) ------------------------------------------
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-- Wishbone Memory A (simulated external IMEM) --------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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ext_mem_a_access: process(clk_gen)
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ext_mem_a_access: process(clk_gen)
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begin
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begin
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if rising_edge(clk_gen) then
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if rising_edge(clk_gen) then
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-- control --
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-- control --
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| Line 362... |
Line 383... |
end if;
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end if;
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end if;
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end if;
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end process ext_mem_a_access;
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end process ext_mem_a_access;
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-- Wishbone Memory B (simulated external memory) ------------------------------------------
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-- Wishbone Memory B (simulated external DMEM) --------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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ext_mem_b_access: process(clk_gen)
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ext_mem_b_access: process(clk_gen)
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begin
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begin
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if rising_edge(clk_gen) then
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if rising_edge(clk_gen) then
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-- control --
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-- control --
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| Line 402... |
Line 423... |
end if;
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end if;
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end if;
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end if;
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end process ext_mem_b_access;
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end process ext_mem_b_access;
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-- Wishbone Memory C (simulated external IO) ----------------------------------------------
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-- -------------------------------------------------------------------------------------------
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ext_mem_c_access: process(clk_gen)
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begin
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if rising_edge(clk_gen) then
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-- control --
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ext_mem_c.ack(0) <= wb_mem_c.cyc and wb_mem_c.stb; -- wishbone acknowledge
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-- write access --
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if ((wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.we) = '1') then -- valid write access
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for i in 0 to 3 loop
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if (wb_mem_c.sel(i) = '1') then
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ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_c.wdata(7+i*8 downto 0+i*8);
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end if;
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end loop; -- i
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end if;
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-- read access --
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ext_mem_c.rdata(0) <= ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2)))); -- word aligned
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-- virtual read and ack latency --
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if (ext_mem_c_latency_c > 1) then
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for i in 1 to ext_mem_c_latency_c-1 loop
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ext_mem_c.rdata(i) <= ext_mem_c.rdata(i-1);
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ext_mem_c.ack(i) <= ext_mem_c.ack(i-1) and wb_mem_c.cyc;
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end loop;
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end if;
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-- error to simulate interrupted LOCKED/EXCLUSIVE bus access --
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wb_mem_c.err <= wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.lock and wb_mem_c.addr(2); -- locked access to odd word-addresses will fail
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-- bus output register --
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if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') then
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wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1);
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wb_mem_c.ack <= '1';
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else
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wb_mem_c.rdata <= (others => '0');
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wb_mem_c.ack <= '0';
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end if;
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end if;
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end process ext_mem_c_access;
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end neorv32_tb_rtl;
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end neorv32_tb_rtl;
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No newline at end of file
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No newline at end of file
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