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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Default Testbench >> #
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-- # << NEORV32 - Default Testbench >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Use the "User Configuration" section to configure the testbench according to your need. #
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-- # The processor is configured to use a maximum of functional units (for testing purpose). #
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-- # Use the "User Configuration" section to configure the testbench according to your needs. #
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-- # See NEORV32 data sheet (docs/NEORV32.pdf) for more information. #
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-- # See NEORV32 data sheet (docs/NEORV32.pdf) for more information. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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| Line 202... |
Line 203... |
MEM_INT_DMEM_SIZE => dmem_size_c, -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE => dmem_size_c, -- size of processor-internal data memory in bytes
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-- Internal Cache memory --
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-- Internal Cache memory --
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ICACHE_EN => icache_en_c, -- implement instruction cache
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ICACHE_EN => icache_en_c, -- implement instruction cache
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ICACHE_NUM_BLOCKS => 8, -- i-cache: number of blocks (min 2), has to be a power of 2
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ICACHE_NUM_BLOCKS => 8, -- i-cache: number of blocks (min 2), has to be a power of 2
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ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_ASSOCIATIVITY => 2, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
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-- External memory interface --
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-- External memory interface --
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MEM_EXT_EN => true, -- implement external memory bus interface?
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MEM_EXT_EN => true, -- implement external memory bus interface?
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
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IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
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IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
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Line 498... |
end process ext_mem_c_access;
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end process ext_mem_c_access;
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-- Wishbone IRQ Triggers ------------------------------------------------------------------
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-- Wishbone IRQ Triggers ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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ext_irq_trigger: process(clk_gen)
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irq_trigger: process(clk_gen)
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begin
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begin
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if rising_edge(clk_gen) then
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if rising_edge(clk_gen) then
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-- default --
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-- default --
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msi_ring <= '0';
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msi_ring <= '0';
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wb_msi.rdata <= (others => '0');
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wb_msi.rdata <= (others => '0');
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| Line 521... |
Line 523... |
if ((wb_mei.cyc and wb_mei.stb and wb_mei.we) = '1') then
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if ((wb_mei.cyc and wb_mei.stb and wb_mei.we) = '1') then
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mei_ring <= '1';
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mei_ring <= '1';
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wb_mei.ack <= '1';
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wb_mei.ack <= '1';
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end if;
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end if;
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end if;
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end if;
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end process ext_irq_trigger;
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end process irq_trigger;
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end neorv32_tb_rtl;
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end neorv32_tb_rtl;
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