| Line 71... |
Line 71... |
constant ext_mem_b_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
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constant ext_mem_b_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
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-- simulated external Wishbone memory C (can be used as external IO) --
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-- simulated external Wishbone memory C (can be used as external IO) --
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constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
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constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
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constant ext_mem_c_size_c : natural := 64; -- wishbone memory size in bytes
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constant ext_mem_c_size_c : natural := 64; -- wishbone memory size in bytes
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constant ext_mem_c_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
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constant ext_mem_c_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
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-- machine interrupt triggers --
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-- simulation interrupt trigger --
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constant msi_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000000"; -- machine software interrupt
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constant irq_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000000";
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constant mei_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000004"; -- machine external interrupt
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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|
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-- internals - hands off! --
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-- internals - hands off! --
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constant int_imem_c : boolean := not ext_imem_c;
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constant int_imem_c : boolean := not ext_imem_c;
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constant int_dmem_c : boolean := not ext_dmem_c;
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constant int_dmem_c : boolean := not ext_dmem_c;
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| Line 107... |
Line 106... |
-- spi --
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-- spi --
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signal spi_data : std_ulogic;
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signal spi_data : std_ulogic;
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|
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-- irq --
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-- irq --
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signal msi_ring, mei_ring : std_ulogic;
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signal msi_ring, mei_ring : std_ulogic;
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signal soc_firq_ring : std_ulogic_vector(3 downto 0);
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|
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-- Wishbone bus --
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-- Wishbone bus --
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type wishbone_t is record
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type wishbone_t is record
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addr : std_ulogic_vector(31 downto 0); -- address
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addr : std_ulogic_vector(31 downto 0); -- address
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wdata : std_ulogic_vector(31 downto 0); -- master write data
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wdata : std_ulogic_vector(31 downto 0); -- master write data
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| Line 122... |
Line 122... |
ack : std_ulogic; -- transfer acknowledge
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ack : std_ulogic; -- transfer acknowledge
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err : std_ulogic; -- transfer error
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err : std_ulogic; -- transfer error
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tag : std_ulogic_vector(2 downto 0); -- tag
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tag : std_ulogic_vector(2 downto 0); -- tag
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lock : std_ulogic; -- locked/exclusive bus access
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lock : std_ulogic; -- locked/exclusive bus access
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end record;
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end record;
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signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_msi, wb_mei : wishbone_t;
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signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t;
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|
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-- Wishbone memories --
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-- Wishbone memories --
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type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0);
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| Line 188... |
Line 188... |
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
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FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
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FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
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-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS => 5, -- number of regions (0..64)
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PMP_NUM_REGIONS => 4, -- number of regions (0..64)
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PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- Hardware Performance Monitors (HPM) --
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS => 12, -- number of inmplemnted HPM counters (0..29)
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HPM_NUM_CNTS => 12, -- number of inmplemnted HPM counters (0..29)
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-- Internal Instruction memory --
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-- Internal Instruction memory --
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MEM_INT_IMEM_EN => int_imem_c , -- implement processor-internal instruction memory
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MEM_INT_IMEM_EN => int_imem_c , -- implement processor-internal instruction memory
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| Line 215... |
Line 215... |
IO_SPI_EN => true, -- implement serial peripheral interface (SPI)?
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IO_SPI_EN => true, -- implement serial peripheral interface (SPI)?
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IO_TWI_EN => true, -- implement two-wire interface (TWI)?
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IO_TWI_EN => true, -- implement two-wire interface (TWI)?
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IO_PWM_EN => true, -- implement pulse-width modulation unit (PWM)?
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IO_PWM_EN => true, -- implement pulse-width modulation unit (PWM)?
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IO_WDT_EN => true, -- implement watch dog timer (WDT)?
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IO_WDT_EN => true, -- implement watch dog timer (WDT)?
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IO_TRNG_EN => false, -- trng cannot be simulated
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IO_TRNG_EN => false, -- trng cannot be simulated
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IO_CFU0_EN => true, -- implement custom functions unit 0 (CFU0)?
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IO_CFS_EN => true, -- implement custom functions subsystem (CFS)?
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IO_CFU1_EN => true -- implement custom functions unit 1 (CFU1)?
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IO_CFS_CONFIG => (others => '0') -- custom CFS configuration generic
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)
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)
|
port map (
|
port map (
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-- Global control --
|
-- Global control --
|
clk_i => clk_gen, -- global clock, rising edge
|
clk_i => clk_gen, -- global clock, rising edge
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rstn_i => rst_gen, -- global reset, low-active, async
|
rstn_i => rst_gen, -- global reset, low-active, async
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| Line 253... |
Line 253... |
-- TWI --
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-- TWI --
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twi_sda_io => twi_sda, -- twi serial data line
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twi_sda_io => twi_sda, -- twi serial data line
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twi_scl_io => twi_scl, -- twi serial clock line
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twi_scl_io => twi_scl, -- twi serial clock line
|
-- PWM --
|
-- PWM --
|
pwm_o => open, -- pwm channels
|
pwm_o => open, -- pwm channels
|
|
-- Custom Functions Subsystem IO --
|
|
cfs_in_i => (others => '0'), -- custom CFS inputs
|
|
cfs_out_o => open, -- custom CFS outputs
|
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
|
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
|
mtime_i => (others => '0'), -- current system time
|
mtime_i => (others => '0'), -- current system time
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-- Interrupts --
|
-- Interrupts --
|
|
soc_firq_i => soc_firq_ring, -- fast interrupt channels
|
mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_EN = false
|
mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_EN = false
|
msw_irq_i => msi_ring, -- machine software interrupt
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msw_irq_i => msi_ring, -- machine software interrupt
|
mext_irq_i => mei_ring -- machine external interrupt
|
mext_irq_i => mei_ring -- machine external interrupt
|
);
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);
|
|
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| Line 345... |
Line 349... |
wb_mem_c.sel <= wb_cpu.sel;
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wb_mem_c.sel <= wb_cpu.sel;
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wb_mem_c.tag <= wb_cpu.tag;
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wb_mem_c.tag <= wb_cpu.tag;
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wb_mem_c.cyc <= wb_cpu.cyc;
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wb_mem_c.cyc <= wb_cpu.cyc;
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wb_mem_c.lock <= wb_cpu.lock;
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wb_mem_c.lock <= wb_cpu.lock;
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|
|
wb_msi.addr <= wb_cpu.addr;
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wb_irq.addr <= wb_cpu.addr;
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wb_msi.wdata <= wb_cpu.wdata;
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wb_irq.wdata <= wb_cpu.wdata;
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wb_msi.we <= wb_cpu.we;
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wb_irq.we <= wb_cpu.we;
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wb_msi.sel <= wb_cpu.sel;
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wb_irq.sel <= wb_cpu.sel;
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wb_msi.tag <= wb_cpu.tag;
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wb_irq.tag <= wb_cpu.tag;
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wb_msi.cyc <= wb_cpu.cyc;
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wb_irq.cyc <= wb_cpu.cyc;
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wb_msi.lock <= wb_cpu.lock;
|
wb_irq.lock <= wb_cpu.lock;
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|
|
wb_mei.addr <= wb_cpu.addr;
|
|
wb_mei.wdata <= wb_cpu.wdata;
|
|
wb_mei.we <= wb_cpu.we;
|
|
wb_mei.sel <= wb_cpu.sel;
|
|
wb_mei.tag <= wb_cpu.tag;
|
|
wb_mei.cyc <= wb_cpu.cyc;
|
|
wb_mei.lock <= wb_cpu.lock;
|
|
|
|
-- CPU read-back signals (no mux here since peripherals have "output gates") --
|
-- CPU read-back signals (no mux here since peripherals have "output gates") --
|
wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_mei.rdata or wb_msi.rdata;
|
wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata;
|
wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_mei.ack or wb_msi.ack;
|
wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_irq.ack;
|
wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_mei.err or wb_msi.err;
|
wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_irq.err;
|
|
|
-- peripheral select via STROBE signal --
|
-- peripheral select via STROBE signal --
|
wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
|
wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
|
wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
|
wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
|
wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
|
wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
|
wb_msi.stb <= wb_cpu.stb when (wb_cpu.addr = msi_trigger_c) else '0';
|
wb_irq.stb <= wb_cpu.stb when (wb_cpu.addr = irq_trigger_c) else '0';
|
wb_mei.stb <= wb_cpu.stb when (wb_cpu.addr = mei_trigger_c) else '0';
|
|
|
|
|
|
-- Wishbone Memory A (simulated external IMEM) --------------------------------------------
|
-- Wishbone Memory A (simulated external IMEM) --------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ext_mem_a_access: process(clk_gen)
|
ext_mem_a_access: process(clk_gen)
|
| Line 501... |
Line 496... |
-- Wishbone IRQ Triggers ------------------------------------------------------------------
|
-- Wishbone IRQ Triggers ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
irq_trigger: process(clk_gen)
|
irq_trigger: process(clk_gen)
|
begin
|
begin
|
if rising_edge(clk_gen) then
|
if rising_edge(clk_gen) then
|
-- default --
|
-- bus interface --
|
|
wb_irq.rdata <= (others => '0');
|
|
wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we;
|
|
wb_irq.err <= '0';
|
|
-- trigger IRQ using CSR.MIE bit layout --
|
msi_ring <= '0';
|
msi_ring <= '0';
|
wb_msi.rdata <= (others => '0');
|
|
wb_msi.ack <= '0';
|
|
wb_msi.err <= '0';
|
|
mei_ring <= '0';
|
mei_ring <= '0';
|
wb_mei.rdata <= (others => '0');
|
soc_firq_ring <= (others => '0');
|
wb_mei.ack <= '0';
|
if ((wb_irq.cyc and wb_irq.stb and wb_irq.we) = '1') then
|
wb_mei.err <= '0';
|
msi_ring <= wb_irq.wdata(03); -- machine software interrupt
|
|
mei_ring <= wb_irq.wdata(11); -- machine software interrupt
|
-- machine software interrupt --
|
soc_firq_ring(0) <= wb_irq.wdata(20); -- fast interrupt channel 4
|
if ((wb_msi.cyc and wb_msi.stb and wb_msi.we) = '1') then
|
soc_firq_ring(1) <= wb_irq.wdata(21); -- fast interrupt channel 5
|
msi_ring <= '1';
|
soc_firq_ring(2) <= wb_irq.wdata(22); -- fast interrupt channel 6
|
wb_msi.ack <= '1';
|
soc_firq_ring(3) <= wb_irq.wdata(22); -- fast interrupt channel 7
|
end if;
|
|
|
|
-- machine external interrupt --
|
|
if ((wb_mei.cyc and wb_mei.stb and wb_mei.we) = '1') then
|
|
mei_ring <= '1';
|
|
wb_mei.ack <= '1';
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process irq_trigger;
|
end process irq_trigger;
|
|
|
|
|
