| Line 106... |
Line 106... |
-- spi --
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-- spi --
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signal spi_data : std_ulogic;
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signal spi_data : std_ulogic;
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-- irq --
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-- irq --
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signal msi_ring, mei_ring : std_ulogic;
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signal msi_ring, mei_ring : std_ulogic;
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signal soc_firq_ring : std_ulogic_vector(3 downto 0);
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signal soc_firq_ring : std_ulogic_vector(7 downto 0);
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-- Wishbone bus --
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-- Wishbone bus --
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type wishbone_t is record
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type wishbone_t is record
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addr : std_ulogic_vector(31 downto 0); -- address
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addr : std_ulogic_vector(31 downto 0); -- address
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wdata : std_ulogic_vector(31 downto 0); -- master write data
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wdata : std_ulogic_vector(31 downto 0); -- master write data
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| Line 166... |
Line 166... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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clk_gen <= not clk_gen after (t_clock_c/2);
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clk_gen <= not clk_gen after (t_clock_c/2);
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rst_gen <= '0', '1' after 60*(t_clock_c/2);
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rst_gen <= '0', '1' after 60*(t_clock_c/2);
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-- CPU Core -------------------------------------------------------------------------------
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-- The Core of the Problem ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_top_inst: neorv32_top
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neorv32_top_inst: neorv32_top
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generic map (
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generic map (
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-- General --
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-- General --
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CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
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| Line 498... |
Line 498... |
irq_trigger: process(clk_gen)
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irq_trigger: process(clk_gen)
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begin
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begin
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if rising_edge(clk_gen) then
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if rising_edge(clk_gen) then
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-- bus interface --
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-- bus interface --
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wb_irq.rdata <= (others => '0');
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wb_irq.rdata <= (others => '0');
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wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we;
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wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel);
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wb_irq.err <= '0';
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wb_irq.err <= '0';
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-- trigger IRQ using CSR.MIE bit layout --
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-- trigger IRQ using CSR.MIE bit layout --
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msi_ring <= '0';
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msi_ring <= '0';
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mei_ring <= '0';
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mei_ring <= '0';
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soc_firq_ring <= (others => '0');
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soc_firq_ring <= (others => '0');
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if ((wb_irq.cyc and wb_irq.stb and wb_irq.we) = '1') then
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if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel)) = '1') then
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msi_ring <= wb_irq.wdata(03); -- machine software interrupt
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msi_ring <= wb_irq.wdata(03); -- machine software interrupt
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mei_ring <= wb_irq.wdata(11); -- machine software interrupt
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mei_ring <= wb_irq.wdata(11); -- machine software interrupt
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soc_firq_ring(0) <= wb_irq.wdata(20); -- fast interrupt channel 4
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soc_firq_ring(0) <= wb_irq.wdata(24); -- fast interrupt SoC channel 0
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soc_firq_ring(1) <= wb_irq.wdata(21); -- fast interrupt channel 5
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soc_firq_ring(1) <= wb_irq.wdata(25); -- fast interrupt SoC channel 1
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soc_firq_ring(2) <= wb_irq.wdata(22); -- fast interrupt channel 6
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soc_firq_ring(2) <= wb_irq.wdata(26); -- fast interrupt SoC channel 2
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soc_firq_ring(3) <= wb_irq.wdata(22); -- fast interrupt channel 7
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soc_firq_ring(3) <= wb_irq.wdata(27); -- fast interrupt SoC channel 3
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soc_firq_ring(4) <= wb_irq.wdata(28); -- fast interrupt SoC channel 4
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soc_firq_ring(5) <= wb_irq.wdata(29); -- fast interrupt SoC channel 5
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soc_firq_ring(6) <= wb_irq.wdata(30); -- fast interrupt SoC channel 6
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soc_firq_ring(7) <= wb_irq.wdata(31); -- fast interrupt SoC channel 7
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end if;
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end if;
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end if;
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end if;
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end process irq_trigger;
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end process irq_trigger;
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