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Line 91... |
-- text.io --
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-- text.io --
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file file_uart0_tx_out : text open write_mode is "neorv32.testbench_uart0.out";
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file file_uart0_tx_out : text open write_mode is "neorv32.testbench_uart0.out";
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file file_uart1_tx_out : text open write_mode is "neorv32.testbench_uart1.out";
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file file_uart1_tx_out : text open write_mode is "neorv32.testbench_uart1.out";
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-- simulation uart0 receiver --
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-- simulation uart0 receiver --
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signal uart0_txd : std_ulogic;
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signal uart0_txd : std_ulogic; -- local loop-back
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signal uart0_cts : std_ulogic; -- local loop-back
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signal uart0_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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signal uart0_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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signal uart0_rx_busy : std_ulogic := '0';
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signal uart0_rx_busy : std_ulogic := '0';
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signal uart0_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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signal uart0_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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signal uart0_rx_baud_cnt : real;
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signal uart0_rx_baud_cnt : real;
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signal uart0_rx_bitcnt : natural;
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signal uart0_rx_bitcnt : natural;
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-- simulation uart1 receiver --
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-- simulation uart1 receiver --
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signal uart1_txd : std_ulogic;
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signal uart1_txd : std_ulogic; -- local loop-back
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signal uart1_cts : std_ulogic; -- local loop-back
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signal uart1_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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signal uart1_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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signal uart1_rx_busy : std_ulogic := '0';
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signal uart1_rx_busy : std_ulogic := '0';
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signal uart1_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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signal uart1_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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signal uart1_rx_baud_cnt : real;
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signal uart1_rx_baud_cnt : real;
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signal uart1_rx_bitcnt : natural;
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signal uart1_rx_bitcnt : natural;
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gpio_o => gpio, -- parallel output
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gpio_o => gpio, -- parallel output
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gpio_i => gpio, -- parallel input
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gpio_i => gpio, -- parallel input
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-- primary UART0 (available if IO_UART0_EN = true) --
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-- primary UART0 (available if IO_UART0_EN = true) --
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uart0_txd_o => uart0_txd, -- UART0 send data
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uart0_txd_o => uart0_txd, -- UART0 send data
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uart0_rxd_i => uart0_txd, -- UART0 receive data
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uart0_rxd_i => uart0_txd, -- UART0 receive data
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uart0_rts_o => uart0_cts, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
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uart0_cts_i => uart0_cts, -- hw flow control: UART0.TX allowed to transmit, low-active, optional
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-- secondary UART1 (available if IO_UART1_EN = true) --
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-- secondary UART1 (available if IO_UART1_EN = true) --
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uart1_txd_o => uart1_txd, -- UART1 send data
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uart1_txd_o => uart1_txd, -- UART1 send data
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uart1_rxd_i => uart1_txd, -- UART1 receive data
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uart1_rxd_i => uart1_txd, -- UART1 receive data
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uart1_rts_o => uart1_cts, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
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uart1_cts_i => uart1_cts, -- hw flow control: UART1.TX allowed to transmit, low-active, optional
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-- SPI (available if IO_SPI_EN = true) --
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-- SPI (available if IO_SPI_EN = true) --
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spi_sck_o => open, -- SPI serial clock
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spi_sck_o => open, -- SPI serial clock
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spi_sdo_o => spi_data, -- controller data out, peripheral data in
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spi_sdo_o => spi_data, -- controller data out, peripheral data in
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spi_sdi_i => spi_data, -- controller data in, peripheral data out
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spi_sdi_i => spi_data, -- controller data in, peripheral data out
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spi_csn_o => open, -- SPI CS
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spi_csn_o => open, -- SPI CS
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