| Line 132... |
Line 132... |
sel : std_ulogic_vector(03 downto 0); -- byte enable
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sel : std_ulogic_vector(03 downto 0); -- byte enable
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stb : std_ulogic; -- strobe
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stb : std_ulogic; -- strobe
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cyc : std_ulogic; -- valid cycle
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cyc : std_ulogic; -- valid cycle
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ack : std_ulogic; -- transfer acknowledge
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ack : std_ulogic; -- transfer acknowledge
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err : std_ulogic; -- transfer error
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err : std_ulogic; -- transfer error
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tag : std_ulogic_vector(03 downto 0); -- request tag
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tag : std_ulogic_vector(02 downto 0); -- request tag
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tag_r : std_ulogic; -- response tag
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lock : std_ulogic; -- exclusive access request
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end record;
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end record;
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signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t;
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signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t;
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-- Wishbone memories --
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-- Wishbone memories --
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type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
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| Line 226... |
Line 226... |
ICACHE_NUM_BLOCKS => 8, -- i-cache: number of blocks (min 2), has to be a power of 2
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ICACHE_NUM_BLOCKS => 8, -- i-cache: number of blocks (min 2), has to be a power of 2
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ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_ASSOCIATIVITY => 2, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
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ICACHE_ASSOCIATIVITY => 2, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
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-- External memory interface --
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-- External memory interface --
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MEM_EXT_EN => true, -- implement external memory bus interface?
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MEM_EXT_EN => true, -- implement external memory bus interface?
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MEM_EXT_TIMEOUT => 255, -- cycles after a pending bus access auto-terminates (0 = disabled)
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
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IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
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IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
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IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART1_EN => true, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_EN => true, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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| Line 256... |
Line 257... |
wb_dat_o => wb_cpu.wdata, -- write data
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wb_dat_o => wb_cpu.wdata, -- write data
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wb_we_o => wb_cpu.we, -- read/write
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wb_we_o => wb_cpu.we, -- read/write
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wb_sel_o => wb_cpu.sel, -- byte enable
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wb_sel_o => wb_cpu.sel, -- byte enable
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wb_stb_o => wb_cpu.stb, -- strobe
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wb_stb_o => wb_cpu.stb, -- strobe
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wb_cyc_o => wb_cpu.cyc, -- valid cycle
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wb_cyc_o => wb_cpu.cyc, -- valid cycle
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wb_tag_i => wb_cpu.tag_r, -- response tag
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wb_lock_o => wb_cpu.lock, -- exclusive access request
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wb_ack_i => wb_cpu.ack, -- transfer acknowledge
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wb_ack_i => wb_cpu.ack, -- transfer acknowledge
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wb_err_i => wb_cpu.err, -- transfer error
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wb_err_i => wb_cpu.err, -- transfer error
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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fence_o => open, -- indicates an executed FENCE operation
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fence_o => open, -- indicates an executed FENCE operation
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fencei_o => open, -- indicates an executed FENCEI operation
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fencei_o => open, -- indicates an executed FENCEI operation
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| Line 445... |
Line 446... |
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-- CPU read-back signals (no mux here since peripherals have "output gates") --
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-- CPU read-back signals (no mux here since peripherals have "output gates") --
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wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata;
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wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata;
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wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_irq.ack;
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wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_irq.ack;
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wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_irq.err;
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wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_irq.err;
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wb_cpu.tag_r <= wb_mem_a.tag_r or wb_mem_b.tag_r or wb_mem_c.tag_r or wb_irq.tag_r;
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-- peripheral select via STROBE signal --
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-- peripheral select via STROBE signal --
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wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
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wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
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wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
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wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
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wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
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wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
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| Line 483... |
Line 483... |
end loop;
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end loop;
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end if;
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end if;
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-- bus output register --
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-- bus output register --
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wb_mem_a.err <= '0';
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wb_mem_a.err <= '0';
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wb_mem_a.tag_r <= '0';
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if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_a.ack = '0') then
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if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_a.ack = '0') then
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wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
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wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
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wb_mem_a.ack <= '1';
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wb_mem_a.ack <= '1';
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else
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else
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wb_mem_a.rdata <= (others => '0');
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wb_mem_a.rdata <= (others => '0');
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| Line 524... |
Line 523... |
end loop;
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end loop;
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end if;
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end if;
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-- bus output register --
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-- bus output register --
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wb_mem_b.err <= '0';
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wb_mem_b.err <= '0';
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wb_mem_b.tag_r <= '0';
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if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_b.ack = '0') then
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if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_b.ack = '0') then
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wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
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wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
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wb_mem_b.ack <= '1';
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wb_mem_b.ack <= '1';
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else
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else
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wb_mem_b.rdata <= (others => '0');
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wb_mem_b.rdata <= (others => '0');
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| Line 565... |
Line 563... |
end loop;
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end loop;
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end if;
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end if;
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-- EXCLUSIVE bus access -----------------------------------------------------
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-- EXCLUSIVE bus access -----------------------------------------------------
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-- -----------------------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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-- make a reservation --
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-- Since there is only one CPU in this design, the exclusive access reservation in THIS memory CANNOT fail.
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if ((wb_mem_c.cyc and wb_mem_c.stb) = '1') and -- valid access
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-- However, this memory module is used to simulated failing LR/SC accesses.
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(wb_mem_c.tag(3) = '1') and -- make a reservation if there is a request (LR.W instruction)
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if ((wb_mem_c.cyc and wb_mem_c.stb) = '1') then -- valid access
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(wb_mem_c.addr(2) = '0') then -- only possible for even word-addresses - odd word-addresses will fail
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ext_mem_c_atomic_reservation <= wb_mem_c.lock; -- make reservation
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ext_mem_c_atomic_reservation <= '1';
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-- clear reservation --
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elsif (wb_mem_c.ack = '1') and -- end of access
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(wb_mem_c.tag(3) = '0') then -- end of exclusive access
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ext_mem_c_atomic_reservation <= '0';
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end if;
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end if;
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-- -----------------------------------------------------------------------------
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-- -----------------------------------------------------------------------------
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-- bus output register --
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-- bus output register --
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wb_mem_c.err <= '0';
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if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') and (wb_mem_c.ack = '0') then
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if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') and (wb_mem_c.ack = '0') then
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wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1);
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wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1);
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wb_mem_c.ack <= '1';
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wb_mem_c.ack <= '1';
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wb_mem_c.tag_r <= ext_mem_c_atomic_reservation;
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wb_mem_c.err <= ext_mem_c_atomic_reservation; -- issue a bus error if there is an exclusive access request
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else
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else
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wb_mem_c.rdata <= (others => '0');
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wb_mem_c.rdata <= (others => '0');
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wb_mem_c.ack <= '0';
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wb_mem_c.ack <= '0';
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wb_mem_c.tag_r <= '0';
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wb_mem_c.err <= '0';
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end if;
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end if;
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end if;
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end if;
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end process ext_mem_c_access;
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end process ext_mem_c_access;
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| Line 601... |
Line 593... |
if rising_edge(clk_gen) then
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if rising_edge(clk_gen) then
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-- bus interface --
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-- bus interface --
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wb_irq.rdata <= (others => '0');
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wb_irq.rdata <= (others => '0');
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wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel);
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wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel);
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wb_irq.err <= '0';
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wb_irq.err <= '0';
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wb_irq.tag_r <= '0';
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-- trigger IRQ using CSR.MIE bit layout --
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-- trigger IRQ using CSR.MIE bit layout --
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msi_ring <= '0';
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msi_ring <= '0';
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mei_ring <= '0';
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mei_ring <= '0';
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soc_firq_ring <= (others => '0');
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soc_firq_ring <= (others => '0');
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if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel)) = '1') then
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if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel)) = '1') then
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