| Line 217... |
Line 217... |
end if;
|
end if;
|
|
|
if ci_mode then
|
if ci_mode then
|
-- No need to send the full expectation in one big chunk
|
-- No need to send the full expectation in one big chunk
|
check_uart(net, uart1_rx_handle, nul & nul);
|
check_uart(net, uart1_rx_handle, nul & nul);
|
check_uart(net, uart1_rx_handle, "0/45" & cr & lf);
|
check_uart(net, uart1_rx_handle, "0/46" & cr & lf);
|
end if;
|
end if;
|
|
|
-- Apply some random data on each SLINK inputs and expect it to
|
-- Apply some random data on each SLINK inputs and expect it to
|
-- be echoed by the CPU. No blocking. Let the SLINK transmitters
|
-- be echoed by the CPU. No blocking. Let the SLINK transmitters
|
-- and receivers do this work in parallel.
|
-- and receivers do this work in parallel.
|
| Line 255... |
Line 255... |
wait_until_idle(net, as_sync(slink_receivers(idx)));
|
wait_until_idle(net, as_sync(slink_receivers(idx)));
|
end loop;
|
end loop;
|
|
|
-- Wait a bit more if some extra unexpected data is produced. If so,
|
-- Wait a bit more if some extra unexpected data is produced. If so,
|
-- uart_rx will fail
|
-- uart_rx will fail
|
wait for (20 * 1e9 / baud0_rate_c) * ns;
|
wait for (20 * (1e9 / baud0_rate_c)) * ns;
|
|
|
test_runner_cleanup(runner);
|
test_runner_cleanup(runner);
|
end process;
|
end process;
|
|
|
-- In case we get stuck waiting there is a watchdog timeout to terminate and fail the
|
-- In case we get stuck waiting there is a watchdog timeout to terminate and fail the
|
| Line 276... |
Line 276... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_top_inst: neorv32_top
|
neorv32_top_inst: neorv32_top
|
generic map (
|
generic map (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
|
USER_CODE => x"12345678", -- custom user code
|
|
HW_THREAD_ID => 0, -- hardware thread id (hartid) (32-bit)
|
HW_THREAD_ID => 0, -- hardware thread id (hartid) (32-bit)
|
INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
-- On-Chip Debugger (OCD) --
|
-- On-Chip Debugger (OCD) --
|
ON_CHIP_DEBUGGER_EN => true, -- implement on-chip debugger
|
ON_CHIP_DEBUGGER_EN => true, -- implement on-chip debugger
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A => true, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A => true, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
|
|
CPU_EXTENSION_RISCV_Zbb => true, -- implement basic bit-manipulation sub-extension?
|
CPU_EXTENSION_RISCV_Zfinx => true, -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx => true, -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
|
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
|
