| Line 113... |
Line 113... |
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-- spi --
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-- spi --
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signal spi_data : std_ulogic;
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signal spi_data : std_ulogic;
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|
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-- irq --
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-- irq --
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signal msi_ring, mei_ring, nmi_ring : std_ulogic;
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signal msi_ring, mei_ring : std_ulogic;
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-- Wishbone bus --
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-- Wishbone bus --
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type wishbone_t is record
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type wishbone_t is record
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addr : std_ulogic_vector(31 downto 0); -- address
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addr : std_ulogic_vector(31 downto 0); -- address
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wdata : std_ulogic_vector(31 downto 0); -- master write data
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wdata : std_ulogic_vector(31 downto 0); -- master write data
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| Line 295... |
Line 295... |
-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
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FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
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FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
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CPU_CNT_WIDTH => 64, -- total width of CPU cycle and instret counters (0..64)
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CPU_CNT_WIDTH => 64, -- total width of CPU cycle and instret counters (0..64)
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-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS => 5, -- number of regions (0..64)
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PMP_NUM_REGIONS => 8, -- number of regions (0..64)
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PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- Hardware Performance Monitors (HPM) --
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS => 12, -- number of implemented HPM counters (0..29)
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HPM_NUM_CNTS => 12, -- number of implemented HPM counters (0..29)
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HPM_CNT_WIDTH => 40, -- total size of HPM counters (0..64)
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HPM_CNT_WIDTH => 40, -- total size of HPM counters (0..64)
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-- Internal Instruction memory --
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-- Internal Instruction memory --
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| Line 406... |
Line 406... |
mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false)
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mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false)
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mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true)
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mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true)
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-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
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-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
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xirq_i => gpio(31 downto 0), -- IRQ channels
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xirq_i => gpio(31 downto 0), -- IRQ channels
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-- CPU Interrupts --
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-- CPU Interrupts --
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nm_irq_i => nmi_ring, -- non-maskable interrupt
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mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_EN = false
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mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_EN = false
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msw_irq_i => msi_ring, -- machine software interrupt
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msw_irq_i => msi_ring, -- machine software interrupt
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mext_irq_i => mei_ring -- machine external interrupt
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mext_irq_i => mei_ring -- machine external interrupt
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);
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);
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| Line 539... |
Line 538... |
end loop;
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end loop;
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end if;
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end if;
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-- bus output register --
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-- bus output register --
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wb_mem_a.err <= '0';
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wb_mem_a.err <= '0';
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if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_a.ack = '0') then
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if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_a.cyc = '1') and (wb_mem_a.ack = '0') then
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wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
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wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
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wb_mem_a.ack <= '1';
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wb_mem_a.ack <= '1';
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else
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else
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wb_mem_a.rdata <= (others => '0');
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wb_mem_a.rdata <= (others => '0');
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wb_mem_a.ack <= '0';
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wb_mem_a.ack <= '0';
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| Line 651... |
Line 650... |
end process ext_mem_c_access;
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end process ext_mem_c_access;
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|
|
|
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-- Wishbone IRQ Triggers ------------------------------------------------------------------
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-- Wishbone IRQ Triggers ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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irq_trigger: process(clk_gen)
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irq_trigger: process(rst_gen, clk_gen)
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begin
|
begin
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if rising_edge(clk_gen) then
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if (rst_gen = '0') then
|
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msi_ring <= '0';
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mei_ring <= '0';
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elsif rising_edge(clk_gen) then
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-- bus interface --
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-- bus interface --
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wb_irq.rdata <= (others => '0');
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wb_irq.rdata <= (others => '0');
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wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel);
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wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel);
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wb_irq.err <= '0';
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wb_irq.err <= '0';
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-- trigger IRQ using CSR.MIE bit layout --
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-- trigger RISC-V platform IRQs --
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nmi_ring <= '0';
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msi_ring <= '0';
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mei_ring <= '0';
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if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel)) = '1') then
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if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel)) = '1') then
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nmi_ring <= wb_irq.wdata(00); -- non-maskable interrupt
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msi_ring <= wb_irq.wdata(03); -- machine software interrupt
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msi_ring <= wb_irq.wdata(03); -- machine software interrupt
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mei_ring <= wb_irq.wdata(11); -- machine software interrupt
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mei_ring <= wb_irq.wdata(11); -- machine software interrupt
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end if;
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end if;
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end if;
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end if;
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end process irq_trigger;
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end process irq_trigger;
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