| Line 5... |
Line 5... |
-- # Use the "User Configuration" section to configure the testbench according to your needs. #
|
-- # Use the "User Configuration" section to configure the testbench according to your needs. #
|
-- # See NEORV32 data sheet for more information. #
|
-- # See NEORV32 data sheet for more information. #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
|
-- # #
|
-- # #
|
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
|
-- # #
|
-- # #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # permitted provided that the following conditions are met: #
|
-- # permitted provided that the following conditions are met: #
|
-- # #
|
-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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| Line 217... |
Line 217... |
end if;
|
end if;
|
|
|
if ci_mode then
|
if ci_mode then
|
-- No need to send the full expectation in one big chunk
|
-- No need to send the full expectation in one big chunk
|
check_uart(net, uart1_rx_handle, nul & nul);
|
check_uart(net, uart1_rx_handle, nul & nul);
|
check_uart(net, uart1_rx_handle, "0/46" & cr & lf);
|
check_uart(net, uart1_rx_handle, "0/45" & cr & lf);
|
end if;
|
end if;
|
|
|
-- Apply some random data on each SLINK inputs and expect it to
|
-- Apply some random data on each SLINK inputs and expect it to
|
-- be echoed by the CPU. No blocking. Let the SLINK transmitters
|
-- be echoed by the CPU. No blocking. Let the SLINK transmitters
|
-- and receivers do this work in parallel.
|
-- and receivers do this work in parallel.
|
| Line 345... |
Line 345... |
IO_CFS_CONFIG => (others => '0'), -- custom CFS configuration generic
|
IO_CFS_CONFIG => (others => '0'), -- custom CFS configuration generic
|
IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits
|
IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits
|
IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits
|
IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits
|
IO_NEOLED_EN => true, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
IO_NEOLED_EN => true, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
IO_NEOLED_TX_FIFO => 8, -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
|
IO_NEOLED_TX_FIFO => 8, -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
|
IO_GPTMR_EN => true -- implement general purpose timer (GPTMR)?
|
IO_GPTMR_EN => true, -- implement general purpose timer (GPTMR)?
|
|
IO_XIP_EN => true -- implement execute in place module (XIP)?
|
)
|
)
|
port map (
|
port map (
|
-- Global control --
|
-- Global control --
|
clk_i => clk_gen, -- global clock, rising edge
|
clk_i => clk_gen, -- global clock, rising edge
|
rstn_i => rst_gen, -- global reset, low-active, async
|
rstn_i => rst_gen, -- global reset, low-active, async
|
| Line 372... |
Line 373... |
wb_ack_i => wb_cpu.ack, -- transfer acknowledge
|
wb_ack_i => wb_cpu.ack, -- transfer acknowledge
|
wb_err_i => wb_cpu.err, -- transfer error
|
wb_err_i => wb_cpu.err, -- transfer error
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
fence_o => open, -- indicates an executed FENCE operation
|
fence_o => open, -- indicates an executed FENCE operation
|
fencei_o => open, -- indicates an executed FENCEI operation
|
fencei_o => open, -- indicates an executed FENCEI operation
|
|
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
|
|
xip_csn_o => open, -- chip-select, low-active
|
|
xip_clk_o => open, -- serial clock
|
|
xip_sdi_i => '1', -- device data input
|
|
xip_sdo_o => open, -- controller data output
|
-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
|
-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
|
slink_tx_dat_o => slink_dat, -- output data
|
slink_tx_dat_o => slink_dat, -- output data
|
slink_tx_val_o => slink_val, -- valid output
|
slink_tx_val_o => slink_val, -- valid output
|
slink_tx_rdy_i => slink_rdy, -- ready to send
|
slink_tx_rdy_i => slink_rdy, -- ready to send
|
-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
|
-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
|
