| Line 67... |
Line 67... |
#define AUTOBOOT_EN (1)
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#define AUTOBOOT_EN (1)
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/** Time until the auto-boot sequence starts (in seconds) */
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/** Time until the auto-boot sequence starts (in seconds) */
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#define AUTOBOOT_TIMEOUT 8
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#define AUTOBOOT_TIMEOUT 8
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/** Set to 0 to disable bootloader status LED */
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/** Set to 0 to disable bootloader status LED */
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#define STATUS_LED_EN (1)
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#define STATUS_LED_EN (1)
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/** SPI_DIRECT_BOOT_EN: Define/uncomment to enable SPI direct boot (disables the entire user console!) */
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//#define SPI_DIRECT_BOOT_EN
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/** Bootloader status LED at GPIO output port */
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/** Bootloader status LED at GPIO output port */
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#define STATUS_LED (0)
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#define STATUS_LED (0)
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/** SPI flash boot image base address (warning! address might wrap-around!) */
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/** SPI flash boot image base address (warning! address might wrap-around!) */
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#define SPI_FLASH_BOOT_ADR (0x00800000)
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#define SPI_FLASH_BOOT_ADR (0x00800000)
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/** SPI flash chip select line at spi_csn_o */
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/** SPI flash chip select line at spi_csn_o */
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| Line 179... |
Line 181... |
/**********************************************************************//**
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/**********************************************************************//**
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* Bootloader main.
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* Bootloader main.
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**************************************************************************/
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**************************************************************************/
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int main(void) {
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int main(void) {
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#ifdef __riscv_compressed
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#warning In order to allow the bootloader to run on any CPU configuration it should be compiled using the base ISA (rv32i/e) only.
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#endif
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// global variable for executable size; 0 means there is no exe available
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exe_available = 0;
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// ------------------------------------------------
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// Minimal CPU hardware initialization
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// - all IO devices are reset and disabled by the crt0 code
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// ------------------------------------------------
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// confiure trap handler (bare-metal, no neorv32 rte available)
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neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&bootloader_trap_handler));
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// ------------------------------------------------
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// ------------------------------------------------
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// Processor hardware initialization
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// Minimal processor hardware initialization
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// - all IO devices are reset and disabled by the crt0 code
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// - all IO devices are reset and disabled by the crt0 code
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// ------------------------------------------------
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// ------------------------------------------------
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// get clock speed (in Hz)
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// get clock speed (in Hz)
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uint32_t clock_speed = SYSINFO_CLK;
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uint32_t clock_speed = SYSINFO_CLK;
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| Line 195... |
Line 213... |
}
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}
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else {
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else {
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neorv32_spi_setup(CLK_PRSC_128, 0, 0, 0);
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neorv32_spi_setup(CLK_PRSC_128, 0, 0, 0);
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}
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}
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if (STATUS_LED_EN == 1) {
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// activate status LED, clear all others
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neorv32_gpio_port_set(1 << STATUS_LED);
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}
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// init UART (no interrupts)
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// init UART (no interrupts)
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neorv32_uart_setup(BAUD_RATE, 0, 0);
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neorv32_uart_setup(BAUD_RATE, 0, 0);
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// Configure machine system timer interrupt for ~2Hz
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// Configure machine system timer interrupt for ~2Hz
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neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (clock_speed/4));
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neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (clock_speed/4));
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// confiure trap handler (bare-metal, no neorv32 rte available)
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neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&bootloader_trap_handler));
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neorv32_cpu_csr_write(CSR_MIE, 1 << CPU_MIE_MTIE); // activate MTIME IRQ source
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neorv32_cpu_csr_write(CSR_MIE, 1 << CPU_MIE_MTIE); // activate MTIME IRQ source
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neorv32_cpu_eint(); // enable global interrupts
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neorv32_cpu_eint(); // enable global interrupts
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if (STATUS_LED_EN == 1) {
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// activate status LED, clear all others
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neorv32_gpio_port_set(1 << STATUS_LED);
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}
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// global variable to executable size; 0 means there is no exe available
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// ------------------------------------------------
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exe_available = 0;
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// Fast boot mode: Direct SPI boot
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// Bootloader will directly boot and execute image from SPI memory.
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// No user UART console is available in this mode!
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// ------------------------------------------------
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#ifdef SPI_DIRECT_BOOT_EN
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#warning Compiling bootloader in 'SPI direct boot mode'. Bootloader will directly boot from SPI memory. No user UART console will be available.
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neorv32_uart_print("\nNEORV32 bootloader\nAccessing SPI flash at ");
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print_hex_word((uint32_t)SPI_FLASH_BOOT_ADR);
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neorv32_uart_print("\n");
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get_exe(EXE_STREAM_FLASH);
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neorv32_uart_print("\n");
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start_app();
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return 0;
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#endif
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// ------------------------------------------------
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// ------------------------------------------------
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// Show bootloader intro and system info
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// Show bootloader intro and system info
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// ------------------------------------------------
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// ------------------------------------------------
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| Line 350... |
Line 382... |
if (exe_available == 0) {
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if (exe_available == 0) {
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neorv32_uart_print("No executable available.");
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neorv32_uart_print("No executable available.");
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return;
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return;
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}
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}
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// no need to shut down or reset the used peripherals
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// no need to shut down/reset the used peripherals
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// no need to disable interrupt sources
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// no need to disable interrupt sources
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// -> this will be done by application's crt0
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// -> crt0 will do a clean CPU/processor reset/setup
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// deactivate global IRQs
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// deactivate global IRQs
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neorv32_cpu_dint();
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neorv32_cpu_dint();
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neorv32_uart_print("Booting...\n\n");
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neorv32_uart_print("Booting...\n\n");
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// wait for UART to finish transmitting
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// wait for UART to finish transmitting
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while ((UART_CT & (1<<UART_CT_TX_BUSY)) != 0);
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while ((UART_CT & (1<<UART_CT_TX_BUSY)) != 0);
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// reset performance counters (to benchmark actual application)
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asm volatile ("csrw mcycle, zero"); // also clears 'cycle'
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asm volatile ("csrw mcycleh, zero"); // also clears 'cycleh'
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asm volatile ("csrw minstret, zero"); // also clears 'instret'
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asm volatile ("csrw minstreth, zero"); // also clears 'instreth'
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// start app at instruction space base address
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// start app at instruction space base address
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register uint32_t app_base = SYSINFO_ISPACE_BASE;
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register uint32_t app_base = SYSINFO_ISPACE_BASE;
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asm volatile ("jalr zero, %0" : : "r" (app_base));
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asm volatile ("jalr zero, %0" : : "r" (app_base));
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while (1);
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while (1);
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}
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}
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| Line 666... |
Line 692... |
uint8_t uint8[sizeof(uint32_t)];
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uint8_t uint8[sizeof(uint32_t)];
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} data;
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} data;
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data.uint32 = wdata;
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data.uint32 = wdata;
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uint32_t i;
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int i;
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for (i=0; i<4; i++) {
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for (i=0; i<4; i++) {
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spi_flash_write_byte(addr + i, data.uint8[3-i]);
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spi_flash_write_byte(addr + i, data.uint8[3-i]);
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}
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}
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}
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}
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| Line 759... |
Line 785... |
uint8_t uint8[sizeof(uint32_t)];
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uint8_t uint8[sizeof(uint32_t)];
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} address;
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} address;
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address.uint32 = addr;
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address.uint32 = addr;
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neorv32_spi_trans(address.uint8[2]);
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int i;
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neorv32_spi_trans(address.uint8[1]);
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for (i=2; i>=0; i--) {
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neorv32_spi_trans(address.uint8[0]);
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neorv32_spi_trans(address.uint8[i]);
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}
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}
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}
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No newline at end of file
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No newline at end of file
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