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Line 40... |
.section .text
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.section .text
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.balign 4
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.balign 4
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.global _start
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.global _start
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// custom CSRs
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.set CSR_MISPACEBASE, 0xfc4 // CUSTOM (r/-): Base address of instruction memory space (via MEM_ISPACE_BASE generic) */
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.set CSR_MDSPACEBASE, 0xfc5 // CUSTOM (r/-): Base address of data memory space (via MEM_DSPACE_BASE generic) */
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.set CSR_MISPACESIZE, 0xfc6 // CUSTOM (r/-): Total size of instruction memory space in byte (via MEM_ISPACE_SIZE generic) */
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.set CSR_MDSPACESIZE, 0xfc7 // CUSTOM (r/-): Total size of data memory space in byte (via MEM_DSPACE_SIZE generic) */
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// IO region
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// IO region
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.set IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region
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.set IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region
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.set MTIMECMP_LO, 0xFFFFFF98
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.set MTIMECMP_HI, 0xFFFFFF9C
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// SYSINFO
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.set SYSINFO_DSPACE_BASE, 0xFFFFFFF4
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.set SYSINFO_DSPACE_SIZE, 0xFFFFFFFC
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_start:
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_start:
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.cfi_startproc
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.cfi_startproc
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.cfi_undefined ra
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.cfi_undefined ra
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Line 108... |
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// *********************************************************
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// *********************************************************
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// Setup stack pointer
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// Setup stack pointer
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// *********************************************************
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// *********************************************************
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__crt0_stack_pointer_init:
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__crt0_stack_pointer_init:
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csrr x11, CSR_MDSPACEBASE // data memory space base address
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lw x11, SYSINFO_DSPACE_BASE(zero) // data memory space base address
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csrr x12, CSR_MDSPACESIZE // data memory space size
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lw x12, SYSINFO_DSPACE_SIZE(zero) // data memory space size
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add sp, x11, x12
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add sp, x11, x12
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addi sp, sp, -4 // stack pointer = last entry
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addi sp, sp, -4 // stack pointer = last entry
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addi fp, sp, 0 // frame pointer = stack pointer
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addi fp, sp, 0 // frame pointer = stack pointer
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Line 132... |
// *********************************************************
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// *********************************************************
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__crt0_neorv32_rte_init:
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__crt0_neorv32_rte_init:
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la x11, __crt0_neorv32_rte
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la x11, __crt0_neorv32_rte
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csrw mtvec, x11 // set address of first-level exception handler
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csrw mtvec, x11 // set address of first-level exception handler
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csrr x11, CSR_MDSPACEBASE // data memory space base address
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lw x11, SYSINFO_DSPACE_BASE(zero) // data memory space base address
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la x12, __crt0_neorv32_rte_dummy_hanlder
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la x12, __crt0_neorv32_rte_dummy_hanlder
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li x13, 2*16 // number of entries (16xEXC, 16xIRQ)
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li x13, 2*16 // number of entries (16xEXC, 16xIRQ)
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__crt0_neorv32_rte_init_loop:
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__crt0_neorv32_rte_init_loop:
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sw x12, 0(x11) // set dummy handler
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sw x12, 0(x11) // set dummy handler
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Line 156... |
__crt0_reset_io_loop:
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__crt0_reset_io_loop:
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sw zero, 0(x11)
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sw zero, 0(x11)
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addi x11, x11, 4
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addi x11, x11, 4
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bne zero, x11, __crt0_reset_io_loop
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bne zero, x11, __crt0_reset_io_loop
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// set mtime_compare to MAX (to prevent an IRQ)
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li x11, -1
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sw x11, MTIMECMP_LO(zero)
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sw x11, MTIMECMP_HI(zero)
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// *********************************************************
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// *********************************************************
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// Clear .bss section (byte-wise)
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// Clear .bss section (byte-wise)
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// *********************************************************
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// *********************************************************
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__crt0_clear_bss:
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__crt0_clear_bss:
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Line 216... |
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// *********************************************************
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// *********************************************************
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// NEORV32 runtime environment: First-level exception/interrupt handler
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// NEORV32 runtime environment: First-level exception/interrupt handler
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// *********************************************************
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// *********************************************************
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.align 4
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__crt0_neorv32_rte:
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__crt0_neorv32_rte:
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// --------------------------------------------
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// --------------------------------------------
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// full context save
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// full context save
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// --------------------------------------------
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// --------------------------------------------
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Line 269... |
// --------------------------------------------
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// --------------------------------------------
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csrr t0, mcause // get cause code
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csrr t0, mcause // get cause code
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andi t1, t0, 0x0f // isolate cause ID
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andi t1, t0, 0x0f // isolate cause ID
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slli t1, t1, 2 // make address offset
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slli t1, t1, 2 // make address offset
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csrr ra, CSR_MDSPACEBASE // data memory space base address
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lw ra, SYSINFO_DSPACE_BASE(zero) // data memory space base address
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add t1, t1, ra // get vetor table entry address (EXC vectors)
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add t1, t1, ra // get vetor table entry address (EXC vectors)
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csrr ra, mepc // get return address
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csrr ra, mepc // get return address
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blt t0, zero, __crt0_neorv32_rte_is_irq // branch if this is an INTERRUPT
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blt t0, zero, __crt0_neorv32_rte_is_irq // branch if this is an INTERRUPT
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