URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [common/] [crt0.S] - Diff between revs 14 and 19

Rev 14	Rev 19
Line 66...	Line 66...
`addi x5, x4, 0`	`addi x5, x4, 0`
`addi x6, x5, 0`	`addi x6, x5, 0`
`addi x7, x6, 0`	`addi x7, x6, 0`
`addi x8, x7, 0`	`addi x8, x7, 0`
`addi x9, x8, 0`	`addi x9, x8, 0`
`addi x10, x9, 0`	`//addi x10, x9, 0`
`addi x11, x10, 0`	`//addi x11, x10, 0`
`addi x12, x11, 0`	`//addi x12, x11, 0`
`addi x13, x12, 0`	`//addi x13, x12, 0`
`addi x14, x13, 0`	`//addi x14, x13, 0`
`addi x15, x14, 0`	`addi x15, x14, 0`

`// the following registers do not exist in rv32e`	`// since we dont know here if we are compiling for a rv32e architecture`
`// "__RISCV_EMBEDDED_CPU__" is automatically defined by the makefiles when`	`// we won't touch registers above x15`
`// compiling for a rv32e* architecture`
`#ifndef __RISCV_EMBEDDED_CPU__`
`addi x16, x15, 0`
`addi x17, x16, 0`
`addi x18, x17, 0`
`addi x19, x18, 0`
`addi x20, x19, 0`
`addi x21, x20, 0`
`addi x22, x21, 0`
`addi x23, x22, 0`
`addi x24, x23, 0`
`addi x25, x24, 0`
`addi x26, x25, 0`
`addi x27, x26, 0`
`addi x28, x27, 0`
`addi x29, x28, 0`
`addi x30, x29, 0`
`addi x31, x30, 0`
`#endif`


`// *********************************************************`	`// *********************************************************`
`// TEST AREA / DANGER ZONE`	`// TEST AREA / DANGER ZONE`
`// *********************************************************`	`// *********************************************************`