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/* ################################################################################################# */
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/* ################################################################################################# */
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/* # << NEORV32 - crt0.S - Start-Up Code >> # */
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/* # << NEORV32 - crt0.S - Start-Up Code >> # */
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/* # ********************************************************************************************* # */
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/* # ********************************************************************************************* # */
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/* # BSD 3-Clause License # */
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/* # BSD 3-Clause License # */
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/* # # */
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/* # # */
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/* # Copyright (c) 2020, Stephan Nolting. All rights reserved. # */
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/* # Copyright (c) 2021, Stephan Nolting. All rights reserved. # */
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/* # # */
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/* # # */
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/* # Redistribution and use in source and binary forms, with or without modification, are # */
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/* # Redistribution and use in source and binary forms, with or without modification, are # */
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/* # permitted provided that the following conditions are met: # */
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/* # permitted provided that the following conditions are met: # */
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/* # # */
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/* # # */
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/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */
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/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */
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#endif
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#endif
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#endif
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#endif
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// *********************************************************
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// *********************************************************
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// Clear floating-point register file (if F extension enabled)
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// *********************************************************
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#ifdef __riscv_flen
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// DO NOT DO THIS if compiling bootloader (to save some program space)
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#ifndef make_bootloader
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fmv.s.x f0, x0
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fmv.s.x f1, x0
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fmv.s.x f2, x0
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fmv.s.x f3, x0
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fmv.s.x f4, x0
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fmv.s.x f5, x0
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fmv.s.x f6, x0
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fmv.s.x f7, x0
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fmv.s.x f8, x0
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fmv.s.x f9, x0
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fmv.s.x f10, x0
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fmv.s.x f11, x0
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fmv.s.x f12, x0
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fmv.s.x f13, x0
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fmv.s.x f14, x0
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fmv.s.x f15, x0
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fmv.s.x f16, x0
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fmv.s.x f17, x0
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fmv.s.x f18, x0
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fmv.s.x f19, x0
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fmv.s.x f20, x0
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fmv.s.x f21, x0
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fmv.s.x f22, x0
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fmv.s.x f23, x0
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fmv.s.x f24, x0
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fmv.s.x f25, x0
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fmv.s.x f26, x0
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fmv.s.x f27, x0
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fmv.s.x f28, x0
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fmv.s.x f29, x0
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fmv.s.x f30, x0
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fmv.s.x f31, x0
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#endif
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#endif
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// *********************************************************
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// No interrupts, thanks
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// No interrupts, thanks
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// *********************************************************
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// *********************************************************
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__crt0_status_init:
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__crt0_status_init:
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li x10, 0x00001800 // clear mstatus and set mpp(1:0)
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li x10, 0x00001800 // clear mstatus and set mpp(1:0)
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csrrw zero, mstatus, x10
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csrrw zero, mstatus, x10
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addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions
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addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions
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csrw mepc, x8
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csrw mepc, x8
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__crt0_dummy_trap_handler_irq:
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__crt0_dummy_trap_handler_irq:
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lw x9, 0(sp)
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lw x8, 0(sp)
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lw x8, 4(sp)
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lw x9, 4(sp)
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addi sp, sp, +8
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addi sp, sp, +8
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mret
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mret
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.cfi_endproc
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.cfi_endproc
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