| Line 68... |
Line 68... |
// Setup CPU core CSRs (some of them DO NOT have a dedicated
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// Setup CPU core CSRs (some of them DO NOT have a dedicated
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// reset and need to be explicitly initialized)
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// reset and need to be explicitly initialized)
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// ************************************************************************************************
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// ************************************************************************************************
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__crt0_cpu_csr_init:
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__crt0_cpu_csr_init:
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la x10, __crt0_dummy_trap_handler // configure early trap handler
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la x10, __crt0_dummy_trap_handler // configure early-boot trap handler
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csrw mtvec, x10
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csrw mtvec, x10
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csrw mepc, x10 // just to init mepc
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csrw mepc, x10 // just to init mepc
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csrw mstatus, zero // disable global IRQ
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csrw mstatus, zero // clear all control flags, also disable global IRQ
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csrw mie, zero // absolutely no interrupt sources, thanks
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csrw mie, zero // absolutely no interrupts sources, thanks
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csrw mip, zero // clear all pending interrupts
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csrw 0x320, zero // stop all counters; use "mcountinhibit" literal address for lagacy toolchain compatibility
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csrw mcounteren, zero // no access from less-privileged modes to counter CSRs
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csrw mcounteren, zero // no access from less-privileged modes to counter CSRs
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li x11, ~5 // stop all counters except for [m]cycle[h] and [m]instret[h]
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csrw mcycle, zero // reset cycle counter
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csrw 0x320, x11 // = mcountinhibit (literal address for lagacy toolchain compatibility)
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csrw mcycle, zero // reset cycle counters
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csrw mcycleh, zero
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csrw mcycleh, zero
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csrw minstret, zero // reset instruction counters
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csrw minstret, zero // reset instructions-retired counter
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csrw minstreth, zero
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csrw minstreth, zero
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// ************************************************************************************************
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// ************************************************************************************************
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// Initialize integer register file (lower half)
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// Initialize integer register file (lower half)
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| Line 105... |
Line 103... |
//addi x9, x0, 0 // implicitly initialized within crt0
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//addi x9, x0, 0 // implicitly initialized within crt0
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//addi x10, x0, 0 // implicitly initialized within crt0
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//addi x10, x0, 0 // implicitly initialized within crt0
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//addi x11, x0, 0 // implicitly initialized within crt0
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//addi x11, x0, 0 // implicitly initialized within crt0
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//addi x12, x0, 0 // implicitly initialized within crt0
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//addi x12, x0, 0 // implicitly initialized within crt0
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//addi x13, x0, 0 // implicitly initialized within crt0
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//addi x13, x0, 0 // implicitly initialized within crt0
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addi x14, x0, 0
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//addi x14, x0, 0 // implicitly initialized within crt0
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addi x15, x0, 0
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//addi x15, x0, 0 // implicitly initialized within crt0
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// ************************************************************************************************
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// ************************************************************************************************
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// Initialize integer register file (upper half, if no E extension)
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// Initialize integer register file (upper half, if no E extension)
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// ************************************************************************************************
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// ************************************************************************************************
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| Line 151... |
Line 149... |
addi x8, x8, 4
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addi x8, x8, 4
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bne x8, x9, __crt0_reset_io_loop
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bne x8, x9, __crt0_reset_io_loop
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// ************************************************************************************************
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// ************************************************************************************************
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// Clear .bss section (byte-wise) using linker script symbols
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// ************************************************************************************************
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__crt0_clear_bss:
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la x11, __crt0_bss_start
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la x12, __crt0_bss_end
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__crt0_clear_bss_loop:
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bge x11, x12, __crt0_clear_bss_loop_end
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sb zero, 0(x11)
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addi x11, x11, 1
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j __crt0_clear_bss_loop
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__crt0_clear_bss_loop_end:
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// ************************************************************************************************
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// Copy initialized .data section from ROM to RAM (byte-wise)
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// Copy initialized .data section from ROM to RAM (byte-wise)
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// ************************************************************************************************
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// ************************************************************************************************
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__crt0_copy_data:
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__crt0_copy_data:
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la x11, __crt0_copy_data_src_begin // start of data area (copy source)
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la x11, __crt0_copy_data_src_begin // start of data area (copy source)
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la x12, __crt0_copy_data_dst_begin // start of data area (copy destination)
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la x12, __crt0_copy_data_dst_begin // start of data area (copy destination)
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| Line 186... |
Line 168... |
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__crt0_copy_data_loop_end:
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__crt0_copy_data_loop_end:
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// ************************************************************************************************
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// ************************************************************************************************
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// Clear .bss section (byte-wise)
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// ************************************************************************************************
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__crt0_clear_bss:
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la x14, __crt0_bss_start
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la x15, __crt0_bss_end
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__crt0_clear_bss_loop:
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bge x14, x15, __crt0_clear_bss_loop_end
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sb zero, 0(x14)
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addi x14, x14, 1
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j __crt0_clear_bss_loop
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__crt0_clear_bss_loop_end:
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// ************************************************************************************************
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// Setup arguments and call main function
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// Setup arguments and call main function
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// ************************************************************************************************
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// ************************************************************************************************
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__crt0_main_entry:
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__crt0_main_entry:
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addi a0, zero, 0 // a0 = argc = 0
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addi a0, zero, 0 // a0 = argc = 0
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addi a1, zero, 0 // a1 = argv = 0
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addi a1, zero, 0 // a1 = argv = 0
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| Line 218... |
Line 216... |
// ************************************************************************************************
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// ************************************************************************************************
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// go to endless sleep mode
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// go to endless sleep mode
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// ************************************************************************************************
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// ************************************************************************************************
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__crt0_shutdown:
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__crt0_shutdown:
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csrci mstatus, 8 // disable global IRQs (clear mstatus.mie)
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csrci mstatus, 8 // disable global IRQs (clear mstatus.mie)
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__crt0_shutdown_loop:
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wfi // go to sleep mode
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wfi // go to sleep mode
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j __crt0_shutdown_loop // endless loop
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j . // endless loop
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// ************************************************************************************************
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// ************************************************************************************************
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// dummy trap handler (for exceptions & IRQs during very early boot stage)
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// dummy trap handler (for exceptions & IRQs during very early boot stage)
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// does nothing but trying to move on to the next instruction
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// does nothing but trying to move on to the next instruction
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