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// #################################################################################################
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// #################################################################################################
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// # << NEORV32 - RISC-V Bit-Manipulation 'B' Extension Test Program >> #
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// # << NEORV32 - RISC-V Bit-Manipulation 'B' Extension Test Program >> #
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// # ********************************************************************************************* #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # BSD 3-Clause License #
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// # #
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// # #
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// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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// # #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # permitted provided that the following conditions are met: #
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// # #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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/**@{*/
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/**@{*/
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/** UART BAUD rate */
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/** UART BAUD rate */
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#define BAUD_RATE (19200)
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#define BAUD_RATE (19200)
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//** Number of test cases for each instruction */
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//** Number of test cases for each instruction */
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#define NUM_TEST_CASES (1000000)
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#define NUM_TEST_CASES (1000000)
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//** Enable Zbb tests when 1 */
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#define ENABLE_ZBB (1)
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//** Enable Zba tests when 1 */
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#define ENABLE_ZBA (1)
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//** Enable Zbs tests when 1 */
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#define ENABLE_ZBS (1)
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//** Enable Zbc tests when 1 */
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#define ENABLE_ZBC (1)
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/**@}*/
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/**@}*/
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// Prototypes
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// Prototypes
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uint32_t xorshift32(void);
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uint32_t xorshift32(void);
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uint32_t check_result(uint32_t num, uint32_t opa, uint32_t opb, uint32_t ref, uint32_t res);
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uint32_t check_result(uint32_t num, uint32_t opa, uint32_t opb, uint32_t ref, uint32_t res);
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void print_report(int num_err, int num_tests);
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void print_report(int num_err, int num_tests);
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/**********************************************************************//**
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/**********************************************************************//**
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* Main function; test all available operations of the NEORV32 'Zbb' extensions
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* Main function; test all available operations of the NEORV32 'B' extension
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* using bit manipulation intrinsics and software-only reference functions (emulation).
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* using bit manipulation intrinsics and software-only reference functions (emulation).
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*
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*
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* @note This program requires the bit-manipulation CPU extension.
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* @note This program requires the bit-manipulation CPU extension.
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*
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*
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* @return Irrelevant.
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* @return Irrelevant.
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const uint32_t num_tests = (int)NUM_TEST_CASES;
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const uint32_t num_tests = (int)NUM_TEST_CASES;
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// capture all exceptions and give debug info via UART
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// capture all exceptions and give debug info via UART
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neorv32_rte_setup();
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neorv32_rte_setup();
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// init UART at default baud rate, no parity bits, ho hw flow control
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// init UART at default baud rate, no parity bits, no hw flow control
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neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
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neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
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// Disable compilation by default
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// Disable compilation by default
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#ifndef RUN_CHECK
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#ifndef RUN_CHECK
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#warning Program HAS NOT BEEN COMPILED! Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.
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#warning Program HAS NOT BEEN COMPILED! Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.
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return 1;
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return 1;
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#endif
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#endif
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// intro
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// intro
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neorv32_uart0_printf("NEORV32 Bit-Manipulation Extension Test (Zba, Zbb)\n\n");
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neorv32_uart0_printf("<<< NEORV32 Bit-Manipulation Extension ('B') Test >>>\n\n");
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// check available hardware extensions and compare with compiler flags
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// check available hardware extensions and compare with compiler flags
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neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
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neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
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// check if Zbb extension is implemented at all
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// check if B extension is implemented at all
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if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_B)) == 0) {
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if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_B)) == 0) {
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neorv32_uart0_print("Error! <B> extension not synthesized!\n");
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neorv32_uart0_print("Error! B extension not synthesized!\n");
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return 1;
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return 1;
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}
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}
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neorv32_uart0_printf("Starting bit-manipulation extension tests (%i test cases per instruction)...\n\n", num_tests);
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neorv32_uart0_printf("Starting bit-manipulation extension tests (%i test cases per instruction)...\n\n", num_tests);
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neorv32_uart0_printf("-----------------------------------------\n");
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#if (ENABLE_ZBB != 0)
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neorv32_uart0_printf("--------------------------------------------\n");
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neorv32_uart0_printf("Zbb - Basic bit-manipulation instructions\n");
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neorv32_uart0_printf("Zbb - Basic bit-manipulation instructions\n");
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neorv32_uart0_printf("-----------------------------------------\n");
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neorv32_uart0_printf("--------------------------------------------\n");
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// ANDN
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// ANDN
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neorv32_uart0_printf("\nANDN:\n");
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neorv32_uart0_printf("\nANDN:\n");
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err_cnt = 0;
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err_cnt = 0;
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for (i=0;i<num_tests; i++) {
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for (i=0;i<num_tests; i++) {
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Line 335... |
res_sw = riscv_emulate_rev8(opa);
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res_sw = riscv_emulate_rev8(opa);
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res_hw = riscv_intrinsic_rev8(opa);
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res_hw = riscv_intrinsic_rev8(opa);
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err_cnt += check_result(i, opa, 0, res_sw, res_hw);
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err_cnt += check_result(i, opa, 0, res_sw, res_hw);
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}
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}
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print_report(err_cnt, num_tests);
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print_report(err_cnt, num_tests);
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#endif
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#if (ENABLE_ZBA != 0)
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neorv32_uart0_printf("\n\n");
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neorv32_uart0_printf("\n\n");
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neorv32_uart0_printf("-----------------------------------------\n");
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neorv32_uart0_printf("--------------------------------------------\n");
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neorv32_uart0_printf("Zba - Address generation instructions\n");
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neorv32_uart0_printf("Zba - Address-generation instructions\n");
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neorv32_uart0_printf("-----------------------------------------\n");
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neorv32_uart0_printf("--------------------------------------------\n");
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// SH1ADD
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// SH1ADD
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neorv32_uart0_printf("\nSH1ADD:\n");
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neorv32_uart0_printf("\nSH1ADD:\n");
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err_cnt = 0;
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err_cnt = 0;
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for (i=0;i<num_tests; i++) {
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for (i=0;i<num_tests; i++) {
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res_sw = riscv_emulate_sh3add(opa, opb);
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res_sw = riscv_emulate_sh3add(opa, opb);
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res_hw = riscv_intrinsic_sh3add(opa, opb);
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res_hw = riscv_intrinsic_sh3add(opa, opb);
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err_cnt += check_result(i, opa, opb, res_sw, res_hw);
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err_cnt += check_result(i, opa, opb, res_sw, res_hw);
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}
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}
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print_report(err_cnt, num_tests);
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print_report(err_cnt, num_tests);
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#endif
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#if (ENABLE_ZBS != 0)
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neorv32_uart0_printf("\n\n");
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neorv32_uart0_printf("--------------------------------------------\n");
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neorv32_uart0_printf("Zbs - Single-bit instructions\n");
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neorv32_uart0_printf("--------------------------------------------\n");
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// BCLR
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neorv32_uart0_printf("\nBCLR:\n");
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err_cnt = 0;
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for (i=0;i<num_tests; i++) {
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opa = xorshift32();
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opb = xorshift32();
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res_sw = riscv_emulate_bclr(opa, opb);
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res_hw = riscv_intrinsic_bclr(opa, opb);
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err_cnt += check_result(i, opa, opb, res_sw, res_hw);
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}
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print_report(err_cnt, num_tests);
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// BCLRI
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neorv32_uart0_printf("\nBCLRI (imm=20):\n"); // FIXME: static immediate
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err_cnt = 0;
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for (i=0;i<num_tests; i++) {
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opa = xorshift32();
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res_sw = riscv_emulate_bclr(opa, 20);
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res_hw = riscv_intrinsic_bclri20(opa);
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err_cnt += check_result(i, opa, opb, res_sw, res_hw);
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}
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print_report(err_cnt, num_tests);
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// BEXT
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neorv32_uart0_printf("\nBEXT:\n");
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err_cnt = 0;
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for (i=0;i<num_tests; i++) {
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opa = xorshift32();
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opb = xorshift32();
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res_sw = riscv_emulate_bext(opa, opb);
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res_hw = riscv_intrinsic_bext(opa, opb);
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err_cnt += check_result(i, opa, opb, res_sw, res_hw);
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}
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print_report(err_cnt, num_tests);
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// BEXTI
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neorv32_uart0_printf("\nBEXTI (imm=20):\n"); // FIXME: static immediate
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err_cnt = 0;
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for (i=0;i<num_tests; i++) {
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opa = xorshift32();
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res_sw = riscv_emulate_bext(opa, 20);
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res_hw = riscv_intrinsic_bexti20(opa);
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err_cnt += check_result(i, opa, opb, res_sw, res_hw);
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}
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print_report(err_cnt, num_tests);
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// BINV
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neorv32_uart0_printf("\nBINV:\n");
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err_cnt = 0;
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for (i=0;i<num_tests; i++) {
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opa = xorshift32();
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opb = xorshift32();
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res_sw = riscv_emulate_binv(opa, opb);
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res_hw = riscv_intrinsic_binv(opa, opb);
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err_cnt += check_result(i, opa, opb, res_sw, res_hw);
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}
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print_report(err_cnt, num_tests);
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// BINVI
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neorv32_uart0_printf("\nBINVI (imm=20):\n"); // FIXME: static immediate
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err_cnt = 0;
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for (i=0;i<num_tests; i++) {
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opa = xorshift32();
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res_sw = riscv_emulate_binv(opa, 20);
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res_hw = riscv_intrinsic_binvi20(opa);
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err_cnt += check_result(i, opa, opb, res_sw, res_hw);
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}
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print_report(err_cnt, num_tests);
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neorv32_uart0_printf("\nBit manipulation extension tests done.\n");
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// BSET
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neorv32_uart0_printf("\nBSET:\n");
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err_cnt = 0;
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for (i=0;i<num_tests; i++) {
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opa = xorshift32();
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opb = xorshift32();
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res_sw = riscv_emulate_bset(opa, opb);
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res_hw = riscv_intrinsic_bset(opa, opb);
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err_cnt += check_result(i, opa, opb, res_sw, res_hw);
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}
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print_report(err_cnt, num_tests);
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// BSETI
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neorv32_uart0_printf("\nBSETI (imm=20):\n"); // FIXME: static immediate
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err_cnt = 0;
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for (i=0;i<num_tests; i++) {
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opa = xorshift32();
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res_sw = riscv_emulate_bset(opa, 20);
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res_hw = riscv_intrinsic_bseti20(opa);
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err_cnt += check_result(i, opa, opb, res_sw, res_hw);
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}
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print_report(err_cnt, num_tests);
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#endif
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#if (ENABLE_ZBC != 0)
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neorv32_uart0_printf("\n\n");
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neorv32_uart0_printf("--------------------------------------------\n");
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neorv32_uart0_printf("Zbc - Carry-less multiplication instructions\n");
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neorv32_uart0_printf("--------------------------------------------\n");
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neorv32_uart0_printf("\nNOTE: The emulation functions will take quite some time to execute.\n");
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// CLMUL
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neorv32_uart0_printf("\nCLMUL:\n");
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err_cnt = 0;
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for (i=0;i<num_tests; i++) {
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opa = xorshift32();
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opb = xorshift32();
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res_sw = riscv_emulate_clmul(opa, opb);
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res_hw = riscv_intrinsic_clmul(opa, opb);
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err_cnt += check_result(i, opa, opb, res_sw, res_hw);
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}
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print_report(err_cnt, num_tests);
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// CLMULH
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neorv32_uart0_printf("\nCLMULH:\n");
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err_cnt = 0;
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for (i=0;i<num_tests; i++) {
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opa = xorshift32();
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opb = xorshift32();
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res_sw = riscv_emulate_clmulh(opa, opb);
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res_hw = riscv_intrinsic_clmulh(opa, opb);
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err_cnt += check_result(i, opa, opb, res_sw, res_hw);
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}
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print_report(err_cnt, num_tests);
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// CLMULR
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neorv32_uart0_printf("\nCLMULR:\n");
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err_cnt = 0;
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for (i=0;i<num_tests; i++) {
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opa = xorshift32();
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opb = xorshift32();
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res_sw = riscv_emulate_clmulr(opa, opb);
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res_hw = riscv_intrinsic_clmulr(opa, opb);
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err_cnt += check_result(i, opa, opb, res_sw, res_hw);
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}
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print_report(err_cnt, num_tests);
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#endif
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neorv32_uart0_printf("\n\nB extension tests completed.\n");
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return 0;
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return 0;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Pseudo-Random Number Generator (to generate test vectors).
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* Pseudo-Random Number Generator (to generate deterministic test vectors).
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*
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*
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* @return Random data (32-bit).
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* @return Random data (32-bit).
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**************************************************************************/
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**************************************************************************/
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uint32_t xorshift32(void) {
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uint32_t xorshift32(void) {
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Line 596... |
else {
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else {
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neorv32_uart0_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
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neorv32_uart0_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
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}
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}
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}
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}
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No newline at end of file
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No newline at end of file
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/**********************************************************************//**
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* "after-main" handler that is executed after the application's
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* main function returns (called by crt0.S start-up code)
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**************************************************************************/
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int __neorv32_crt0_after_main(int32_t return_code) {
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if (return_code) {
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neorv32_uart0_printf("\n<RTE> main function returned with exit code (%i) </RTE>\n", return_code);
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}
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return 0;
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}
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No newline at end of file
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No newline at end of file
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