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// #################################################################################################
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// #################################################################################################
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// # << NEORV32 - Intrinsics + Emulation Functions for the B CPU extensions >> #
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// # << NEORV32 - Intrinsics + Emulation Functions for the CPU B extension >> #
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// # ********************************************************************************************* #
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// # ********************************************************************************************* #
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// # The intrinsics provided by this library allow to use the hardware bit manipulation unit of #
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// # The intrinsics provided by this library allow to use the hardware bit manipulation unit of #
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// # the RISC-V B CPU extension without the need for B support by the compiler. #
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// # the RISC-V B CPU extension without the need for support by the compiler. #
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// # ********************************************************************************************* #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # BSD 3-Clause License #
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// # #
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// # #
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// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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// # #
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// # #
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/**********************************************************************//**
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/**********************************************************************//**
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* @file bitmanip_test/neorv32_b_extension_intrinsics.h
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* @file bitmanip_test/neorv32_b_extension_intrinsics.h
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* @author Stephan Nolting
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* @author Stephan Nolting
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* @brief "Intrinsic" library for the NEORV32 bit manipulation Zbb extension.
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* @brief "Intrinsic" library for the NEORV32 bit manipulation B extension.
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* Also provides emulation functions for all intrinsics (functionality re-built in pure software).
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* Also provides emulation functions for all intrinsics (functionality re-built in pure software).
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*
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*
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* @warning This library is just a temporary fall-back until the Zbb extensions are supported by the upstream RISC-V GCC port.
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* @warning This library is just a temporary fall-back until the B extension is supported by the upstream RISC-V GCC port.
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**************************************************************************/
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**************************************************************************/
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#ifndef neorv32_b_extension_intrinsics_h
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#ifndef neorv32_b_extension_intrinsics_h
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#define neorv32_b_extension_intrinsics_h
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#define neorv32_b_extension_intrinsics_h
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// ################################################################################################
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// ################################################################################################
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// "Intrinsics"
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// "Intrinsics"
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// ################################################################################################
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// ################################################################################################
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// ---------------------------------------------
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// ================================================================================================
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// Zbb - Base instructions
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// Zbb - Base instructions
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// ---------------------------------------------
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// ================================================================================================
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/**********************************************************************//**
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/**********************************************************************//**
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* Intrinsic: Bit manipulation CLZ (count leading zeros) [B.Zbb]
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* Intrinsic: Bit manipulation CLZ (count leading zeros) [B.Zbb]
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*
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*
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* @param[in] rs1 Source operand 1 (a0).
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* @param[in] rs1 Source operand 1 (a0).
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return result;
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return result;
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}
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}
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// ================================================================================================
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// Zbb - Base instructions
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// ================================================================================================
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/**********************************************************************//**
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* Intrinsic: Address generation instructions SH1ADD (add with logical-1-shift) [B.Zba]
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*
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* @param[in] rs1 Source operand 1 (a0).
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* @param[in] rs2 Source operand 2 (a0).
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* @return Operand 2 + (Operand 1 << 1)
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**************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sh1add(uint32_t rs1, uint32_t rs2) {
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register uint32_t result __asm__ ("a0");
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register uint32_t tmp_a __asm__ ("a0") = rs1;
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register uint32_t tmp_b __asm__ ("a1") = rs2;
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// dummy instruction to prevent GCC "constprop" optimization
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asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
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// sh1add a0, a0, a1
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CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b010, a0, 0b0110011);
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return result;
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}
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/**********************************************************************//**
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* Intrinsic: Address generation instructions SH2ADD (add with logical-2-shift) [B.Zba]
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*
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* @param[in] rs1 Source operand 1 (a0).
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* @param[in] rs2 Source operand 2 (a0).
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* @return Operand 2 + (Operand 1 << 2)
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**************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sh2add(uint32_t rs1, uint32_t rs2) {
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register uint32_t result __asm__ ("a0");
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register uint32_t tmp_a __asm__ ("a0") = rs1;
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register uint32_t tmp_b __asm__ ("a1") = rs2;
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// dummy instruction to prevent GCC "constprop" optimization
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asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
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// sh2add a0, a0, a1
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CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b100, a0, 0b0110011);
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return result;
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}
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/**********************************************************************//**
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* Intrinsic: Address generation instructions SH1ADD (add with logical-3-shift) [B.Zba]
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*
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* @param[in] rs1 Source operand 1 (a0).
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* @param[in] rs2 Source operand 2 (a0).
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* @return Operand 2 + (Operand 1 << 3)
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**************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sh3add(uint32_t rs1, uint32_t rs2) {
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register uint32_t result __asm__ ("a0");
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register uint32_t tmp_a __asm__ ("a0") = rs1;
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register uint32_t tmp_b __asm__ ("a1") = rs2;
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// dummy instruction to prevent GCC "constprop" optimization
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asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
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// sh3add a0, a0, a1
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CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b110, a0, 0b0110011);
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return result;
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}
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// ################################################################################################
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// ################################################################################################
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// Emulation functions
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// Emulation functions
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// ################################################################################################
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// ################################################################################################
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// ---------------------------------------------
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// ================================================================================================
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// Zbb - Base instructions
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// Zbb - Base instructions
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// ---------------------------------------------
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// ================================================================================================
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/**********************************************************************//**
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/**********************************************************************//**
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* Intrinsic: Bit manipulation CLZ (count leading zeros) [emulation]
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* Intrinsic: Bit manipulation CLZ (count leading zeros) [emulation]
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*
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*
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return tmp;
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return tmp;
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}
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}
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// ================================================================================================
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// Zba - Address generation instructions
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// ================================================================================================
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/**********************************************************************//**
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* Intrinsic: Address generation instructions SH1ADD (add with logical-1-shift) [emulation]
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*
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* @param[in] rs1 Source operand 1 (a0).
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* @param[in] rs2 Source operand 1 (a0).
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* @return Operand 2 + (Operand 1 << 1)
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**************************************************************************/
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uint32_t riscv_emulate_sh1add(uint32_t rs1, uint32_t rs2) {
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return rs2 + (rs1 << 1);
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}
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/**********************************************************************//**
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* Intrinsic: Address generation instructions SH2ADD (add with logical-2-shift) [emulation]
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*
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* @param[in] rs1 Source operand 1 (a0).
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* @param[in] rs2 Source operand 1 (a0).
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* @return Operand 2 + (Operand 1 << 2)
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**************************************************************************/
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uint32_t riscv_emulate_sh2add(uint32_t rs1, uint32_t rs2) {
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return rs2 + (rs1 << 2);
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}
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/**********************************************************************//**
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* Intrinsic: Address generation instructions SH3ADD (add with logical-3-shift) [emulation]
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*
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* @param[in] rs1 Source operand 1 (a0).
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* @param[in] rs2 Source operand 1 (a0).
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* @return Operand 2 + (Operand 1 << 3)
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**************************************************************************/
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uint32_t riscv_emulate_sh3add(uint32_t rs1, uint32_t rs2) {
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return rs2 + (rs1 << 3);
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}
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#endif // neorv32_b_extension_intrinsics_h
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#endif // neorv32_b_extension_intrinsics_h
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