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https://opencores.org/ocsvn/neorv32/neorv32/trunk
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Rev 63 |
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Line 121... |
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// check available hardware extensions and compare with compiler flags
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// check available hardware extensions and compare with compiler flags
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neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
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neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
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// check if Zfinx extension is implemented at all
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// check if Zfinx extension is implemented at all
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if (neorv32_cpu_check_zext(CSR_MZEXT_ZFINX) == 0) {
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if ((SYSINFO_CPU & (1<<SYSINFO_CPU_ZFINX)) == 0) {
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neorv32_uart_print("Error! <Zfinx> extension not synthesized!\n");
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neorv32_uart_print("Error! <Zfinx> extension not synthesized!\n");
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return 1;
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return 1;
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}
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}
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neorv32_uart_printf("SILENT_MODE enabled (only showing actual errors)\n");
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neorv32_uart_printf("SILENT_MODE enabled (only showing actual errors)\n");
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#endif
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#endif
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neorv32_uart_printf("Test cases per instruction: %u\n", (uint32_t)NUM_TEST_CASES);
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neorv32_uart_printf("Test cases per instruction: %u\n", (uint32_t)NUM_TEST_CASES);
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neorv32_uart_printf("NOTE: The NEORV32 FPU does not support subnormal numbers yet. Subnormal numbers are flushed to zero.\n\n");
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neorv32_uart_printf("NOTE: The NEORV32 FPU does not support subnormal numbers yet. Subnormal numbers are flushed to zero.\n\n");
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// enable FPU extension
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uint32_t mstatus = neorv32_cpu_csr_read(CSR_MSTATUS);
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mstatus |= 1 << CSR_MSTATUS_FS_L; // state = initial
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neorv32_cpu_csr_write(CSR_MSTATUS, mstatus);
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// clear exception status word
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// clear exception status word
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neorv32_cpu_csr_write(CSR_FFLAGS, 0); // real hardware
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neorv32_cpu_csr_write(CSR_FFLAGS, 0); // real hardware
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feclearexcept(FE_ALL_EXCEPT); // software runtime (GCC floating-point emulation)
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feclearexcept(FE_ALL_EXCEPT); // software runtime (GCC floating-point emulation)
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