| Line 335... |
Line 335... |
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN);
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tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN);
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tmp_a |= (1<<CSR_MCOUNTEREN_CY); // re-allow access right
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tmp_a |= (1<<CSR_MCOUNTEREN_CY); // re-allow access right
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neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a);
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neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a);
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/*
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// ----------------------------------------------------------
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// Execute DRET in M-mode (has to trap!)
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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PRINT_STANDARD("[%i] DRET in M-mode: ", cnt_test);
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// skip if U-mode is not implemented
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if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_U)) {
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cnt_test++;
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asm volatile("dret");
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
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test_ok();
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}
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else {
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test_fail();
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}
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}
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else {
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PRINT_STANDARD("skipped (n.a. without U-ext)\n");
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}
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*/
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/*
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// ----------------------------------------------------------
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// Execute MRET in U-mode (has to trap!)
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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PRINT_STANDARD("[%i] MRET in U-mode: ", cnt_test);
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// skip if U-mode is not implemented
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if (neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CSR_MZEXT_DEBUGMODE)) {
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cnt_test++;
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// switch to user mode (hart will be back in MACHINE mode when trap handler returns)
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neorv32_cpu_goto_user_mode();
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{
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asm volatile("mret");
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}
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
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test_ok();
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}
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else {
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test_fail();
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}
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|
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}
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else {
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PRINT_STANDARD("skipped (n.a. without U-ext)\n");
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}
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*/
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|
|
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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// Test performance counter: setup as many events and counter as feasible
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// Test performance counter: setup as many events and counter as feasible
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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PRINT_STANDARD("[%i] Configuring HPM events: ", cnt_test);
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PRINT_STANDARD("[%i] Configuring HPM events: ", cnt_test);
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| Line 1289... |
Line 1349... |
cnt_test++;
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cnt_test++;
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|
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// program wake-up timer
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// program wake-up timer
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neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + 1000);
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neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + 1000);
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|
// put CPU into sleep mode
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// clear timeout wait flag
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asm volatile ("wfi");
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tmp_a = neorv32_cpu_csr_read(CSR_MSTATUS);
|
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tmp_a &= ~(1 << CSR_MSTATUS_TW);
|
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neorv32_cpu_csr_write(CSR_MSTATUS, tmp_a);
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|
|
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// switch to user mode (hart will be back in MACHINE mode when trap handler returns)
|
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neorv32_cpu_goto_user_mode();
|
|
{
|
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// only when mstatus.TW = 0 executing WFI in user mode is allowed
|
|
asm volatile ("wfi"); // put CPU into sleep mode
|
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}
|
|
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) != TRAP_CODE_MTI) {
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if (neorv32_cpu_csr_read(CSR_MCAUSE) != TRAP_CODE_MTI) {
|
test_fail();
|
test_fail();
|
}
|
}
|
else {
|
else {
|
