| Line 201... |
Line 201... |
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// enable global interrupts
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// enable global interrupts
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neorv32_cpu_eint();
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neorv32_cpu_eint();
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// **********************************************************************************************
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// Run CPU and SoC tests
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// **********************************************************************************************
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// ----------------------------------------------------------
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// Test performance counter: setup as many events and counter as feasible
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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PRINT_STANDARD("[%i] Configuring HPM events: ", cnt_test);
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num_hpm_cnts_global = neorv32_cpu_hpm_get_counters();
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if (num_hpm_cnts_global != 0) {
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cnt_test++;
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER3, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT3, 1 << HPMCNT_EVENT_CIR);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER4, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT4, 1 << HPMCNT_EVENT_WAIT_IF);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER5, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT5, 1 << HPMCNT_EVENT_WAIT_II);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER6, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT6, 1 << HPMCNT_EVENT_WAIT_MC);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER7, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT7, 1 << HPMCNT_EVENT_LOAD);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER8, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT8, 1 << HPMCNT_EVENT_STORE);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER9, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT9, 1 << HPMCNT_EVENT_WAIT_LS);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT10, 1 << HPMCNT_EVENT_JUMP);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT11, 1 << HPMCNT_EVENT_BRANCH);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT12, 1 << HPMCNT_EVENT_TBRANCH);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER13, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT13, 1 << HPMCNT_EVENT_TRAP);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER14, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT14, 1 << HPMCNT_EVENT_ILLEGAL);
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neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); // enable all counters
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// make sure there was no exception
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
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test_ok();
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}
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else {
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test_fail();
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}
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}
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else {
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PRINT_STANDARD("skipped (n.a.)\n");
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}
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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// Test standard RISC-V performance counter [m]cycle[h]
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// Test standard RISC-V performance counter [m]cycle[h]
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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PRINT_STANDARD("[%i] [m]cycle[h] counter: ", cnt_test);
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PRINT_STANDARD("[%i] [m]cycle[h] counter: ", cnt_test);
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| Line 363... |
Line 407... |
PRINT_STANDARD("skipped (n.a. without U-ext)\n");
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PRINT_STANDARD("skipped (n.a. without U-ext)\n");
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}
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}
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*/
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*/
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/*
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// ----------------------------------------------------------
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// Execute MRET in U-mode (has to trap!)
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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PRINT_STANDARD("[%i] MRET in U-mode: ", cnt_test);
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// skip if U-mode is not implemented
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if (neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CSR_MZEXT_DEBUGMODE)) {
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cnt_test++;
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// switch to user mode (hart will be back in MACHINE mode when trap handler returns)
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neorv32_cpu_goto_user_mode();
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{
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asm volatile("mret");
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}
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
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test_ok();
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}
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else {
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test_fail();
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}
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}
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else {
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PRINT_STANDARD("skipped (n.a. without U-ext)\n");
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}
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*/
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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// Test performance counter: setup as many events and counter as feasible
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// Execute MRET in U-mode (has to trap!)
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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PRINT_STANDARD("[%i] Configuring HPM events: ", cnt_test);
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PRINT_STANDARD("[%i] MRET in U-mode: ", cnt_test);
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num_hpm_cnts_global = neorv32_cpu_hpm_get_counters();
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// skip if U-mode is not implemented
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if (SYSINFO_CPU & (1<<SYSINFO_CPU_DEBUGMODE)) {
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if (num_hpm_cnts_global != 0) {
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cnt_test++;
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cnt_test++;
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER3, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT3, 1 << HPMCNT_EVENT_CIR);
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// switch to user mode (hart will be back in MACHINE mode when trap handler returns)
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER4, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT4, 1 << HPMCNT_EVENT_WAIT_IF);
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neorv32_cpu_goto_user_mode();
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER5, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT5, 1 << HPMCNT_EVENT_WAIT_II);
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{
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER6, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT6, 1 << HPMCNT_EVENT_WAIT_MC);
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asm volatile("mret");
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER7, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT7, 1 << HPMCNT_EVENT_LOAD);
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}
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER8, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT8, 1 << HPMCNT_EVENT_STORE);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER9, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT9, 1 << HPMCNT_EVENT_WAIT_LS);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT10, 1 << HPMCNT_EVENT_JUMP);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT11, 1 << HPMCNT_EVENT_BRANCH);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT12, 1 << HPMCNT_EVENT_TBRANCH);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER13, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT13, 1 << HPMCNT_EVENT_TRAP);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER14, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT14, 1 << HPMCNT_EVENT_ILLEGAL);
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neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); // enable all counters
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// make sure there was no exception
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
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test_ok();
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test_ok();
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}
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}
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else {
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else {
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test_fail();
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test_fail();
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}
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}
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}
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}
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else {
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else {
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PRINT_STANDARD("skipped (n.a.)\n");
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PRINT_STANDARD("skipped (n.a. without U-ext)\n");
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}
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}
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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// External memory interface test
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// External memory interface test
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| Line 645... |
Line 648... |
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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PRINT_STANDARD("[%i] I_ILLEG (illegal instr.) EXC: ", cnt_test);
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PRINT_STANDARD("[%i] I_ILLEG (illegal instr.) EXC: ", cnt_test);
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cnt_test++;
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cnt_test++;
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asm volatile ("csrrw zero, 0xfff, zero"); // = 0xfff01073 : CSR 0xfff not implemented -> illegal instruction
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// invalid instruction: using x0=x0 OP x0 with invalid opcode
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CUSTOM_INSTR_R2_TYPE(0b0000000, x0, x0, 0b000, x0, 0b1111111);
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// make sure this has cause an illegal exception
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// make sure this has cause an illegal exception
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
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// make sure this is really the instruction that caused the exception
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// make sure this is really the instruction that caused the exception
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// for illegal instructions mtval contains the actual instruction word
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// for illegal instructions mtval contains the actual instruction word
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if (neorv32_cpu_csr_read(CSR_MTVAL) == 0xfff01073) {
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if (neorv32_cpu_csr_read(CSR_MTVAL) == 0x0000007f) {
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test_ok();
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test_ok();
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}
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}
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else {
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else {
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test_fail();
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test_fail();
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}
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}
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