| Line 1... |
Line 1... |
// #################################################################################################
|
// #################################################################################################
|
// # << NEORV32 - Processor Test Program >> #
|
// # << NEORV32 - Processor Test Program >> #
|
// # ********************************************************************************************* #
|
// # ********************************************************************************************* #
|
// # BSD 3-Clause License #
|
// # BSD 3-Clause License #
|
// # #
|
// # #
|
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
|
// # #
|
// # #
|
// # Redistribution and use in source and binary forms, with or without modification, are #
|
// # Redistribution and use in source and binary forms, with or without modification, are #
|
// # permitted provided that the following conditions are met: #
|
// # permitted provided that the following conditions are met: #
|
// # #
|
// # #
|
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
| Line 53... |
Line 53... |
#define ADDR_UNALIGNED_1 (0x00000001)
|
#define ADDR_UNALIGNED_1 (0x00000001)
|
//** Reachable unaligned address */
|
//** Reachable unaligned address */
|
#define ADDR_UNALIGNED_2 (0x00000002)
|
#define ADDR_UNALIGNED_2 (0x00000002)
|
//** Unreachable word-aligned address */
|
//** Unreachable word-aligned address */
|
#define ADDR_UNREACHABLE (IO_BASE_ADDRESS-4)
|
#define ADDR_UNREACHABLE (IO_BASE_ADDRESS-4)
|
|
//**Read-only word-aligned address */
|
|
#define ADDR_READONLY ((uint32_t)&NEORV32_SYSINFO.CLK)
|
//** external memory base address */
|
//** external memory base address */
|
#define EXT_MEM_BASE (0xF0000000)
|
#define EXT_MEM_BASE (0xF0000000)
|
/**@}*/
|
/**@}*/
|
|
|
|
|
| Line 283... |
Line 285... |
//else {
|
//else {
|
// test_fail();
|
// test_fail();
|
//}
|
//}
|
|
|
|
|
// ----------------------------------------------------------
|
//// ----------------------------------------------------------
|
// Test standard RISC-V performance counter [m]instret[h]
|
//// Test standard RISC-V performance counter [m]instret[h]
|
// ----------------------------------------------------------
|
//// ----------------------------------------------------------
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
//neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
PRINT_STANDARD("[%i] instret counter: ", cnt_test);
|
//PRINT_STANDARD("[%i] instret counter: ", cnt_test);
|
|
//
|
cnt_test++;
|
//cnt_test++;
|
|
//
|
// make sure counter is enabled
|
//// make sure counter is enabled
|
asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_IR));
|
//asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_IR));
|
|
//
|
// prepare overflow
|
//// prepare overflow
|
neorv32_cpu_set_minstret(0x00000000FFFFFFFFULL);
|
//neorv32_cpu_set_minstret(0x00000000FFFFFFFFULL);
|
|
//
|
// get instruction counter HIGH
|
//// get instruction counter HIGH
|
tmp_a = neorv32_cpu_csr_read(CSR_INSTRETH);
|
//tmp_a = neorv32_cpu_csr_read(CSR_INSTRETH);
|
|
//
|
// make sure instruction counter high has incremented and there was no exception during access
|
//// make sure instruction counter high has incremented and there was no exception during access
|
if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {
|
//if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) {
|
test_ok();
|
// test_ok();
|
}
|
//}
|
else {
|
//else {
|
test_fail();
|
// test_fail();
|
}
|
//}
|
|
|
|
|
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
// Test mcountinhibt: inhibit auto-inc of [m]cycle
|
// Test mcountinhibt: inhibit auto-inc of [m]cycle
|
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
| Line 649... |
Line 651... |
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
PRINT_STANDARD("[%i] L_ACC (load bus access) EXC: ", cnt_test);
|
PRINT_STANDARD("[%i] L_ACC (load bus access) EXC: ", cnt_test);
|
cnt_test++;
|
cnt_test++;
|
|
|
|
tmp_a = (1 << BUSKEEPER_ERR_FLAG) | (1 << BUSKEEPER_ERR_TYPE);
|
|
|
// load from unreachable aligned address
|
// load from unreachable aligned address
|
neorv32_cpu_load_unsigned_word(ADDR_UNREACHABLE);
|
neorv32_cpu_load_unsigned_word(ADDR_UNREACHABLE);
|
|
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_L_ACCESS) {
|
if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_L_ACCESS) && // load bus access error exception
|
|
(NEORV32_BUSKEEPER.CTRL = tmp_a)) { // buskeeper: error flag + timeout error
|
test_ok();
|
test_ok();
|
}
|
}
|
else {
|
else {
|
test_fail();
|
test_fail();
|
}
|
}
|
| Line 685... |
Line 690... |
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
PRINT_STANDARD("[%i] S_ACC (store bus access) EXC: ", cnt_test);
|
PRINT_STANDARD("[%i] S_ACC (store bus access) EXC: ", cnt_test);
|
cnt_test++;
|
cnt_test++;
|
|
|
|
tmp_a = (1 << BUSKEEPER_ERR_FLAG) | (0 << BUSKEEPER_ERR_TYPE);
|
|
|
// store to unreachable aligned address
|
// store to unreachable aligned address
|
neorv32_cpu_store_unsigned_word(ADDR_UNREACHABLE, 0);
|
neorv32_cpu_store_unsigned_word(ADDR_READONLY, 0);
|
|
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_S_ACCESS) {
|
if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_S_ACCESS) && // store bus access error exception
|
|
(NEORV32_BUSKEEPER.CTRL == tmp_a)) { // buskeeper: error flag + device error
|
test_ok();
|
test_ok();
|
}
|
}
|
else {
|
else {
|
test_fail();
|
test_fail();
|
}
|
}
|
| Line 1469... |
Line 1477... |
if (neorv32_cpu_csr_read(CSR_MCAUSE) != 0) {
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) != 0) {
|
test_ok();
|
test_ok();
|
}
|
}
|
else {
|
else {
|
test_fail();
|
test_fail();
|
PRINT_STANDARD("answer: 0x%x", neorv32_cpu_csr_read(CSR_MCAUSE));
|
|
}
|
}
|
|
|
// restore original handler
|
// restore original handler
|
neorv32_rte_exception_install(RTE_TRAP_I_ILLEGAL, global_trap_handler);
|
neorv32_rte_exception_install(RTE_TRAP_I_ILLEGAL, global_trap_handler);
|
|
|
| Line 1731... |
Line 1738... |
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
// HPM reports
|
// HPM reports
|
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1); // stop all counters
|
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1); // stop all counters
|
PRINT_STANDARD("\n\n-- HPM reports LOW (%u HPMs available) --\n", num_hpm_cnts_global);
|
PRINT_STANDARD("\n\n-- HPM reports LOW (%u HPMs available) --\n", num_hpm_cnts_global);
|
PRINT_STANDARD("#IR - Instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET)); // = "HPM_0"
|
PRINT_STANDARD("#IR Instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET)); // = "HPM_0"
|
//PRINT_STANDARD("#TM - Time: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_TIME)); // = "HPM_1"
|
//PRINT_STANDARD("#TM Time: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_TIME)); // = "HPM_1"
|
PRINT_STANDARD("#CY - CLKs: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_CYCLE)); // = "HPM_2"
|
PRINT_STANDARD("#CY CLKs: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_CYCLE)); // = "HPM_2"
|
PRINT_STANDARD("#03 - Compr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3));
|
PRINT_STANDARD("#03 Compr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3));
|
PRINT_STANDARD("#04 - IF wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4));
|
PRINT_STANDARD("#04 IF wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4));
|
PRINT_STANDARD("#05 - II wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5));
|
PRINT_STANDARD("#05 II wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5));
|
PRINT_STANDARD("#06 - ALU wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6));
|
PRINT_STANDARD("#06 ALU wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6));
|
PRINT_STANDARD("#07 - Loads: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7));
|
PRINT_STANDARD("#07 Loads: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7));
|
PRINT_STANDARD("#08 - Stores: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8));
|
PRINT_STANDARD("#08 Stores: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8));
|
PRINT_STANDARD("#09 - MEM wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9));
|
PRINT_STANDARD("#09 MEM wait: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9));
|
PRINT_STANDARD("#10 - Jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10));
|
PRINT_STANDARD("#10 Jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10));
|
PRINT_STANDARD("#11 - Branches: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11));
|
PRINT_STANDARD("#11 Branches: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11));
|
PRINT_STANDARD("#12 - Taken: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12));
|
PRINT_STANDARD("#12 - Taken: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12));
|
PRINT_STANDARD("#13 - Traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13));
|
PRINT_STANDARD("#13 Traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13));
|
PRINT_STANDARD("#14 - Illegals: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER14));
|
PRINT_STANDARD("#14 Illegals: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER14));
|
|
|
|
|
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
// Final test reports
|
// Final test reports
|
// ----------------------------------------------------------
|
// ----------------------------------------------------------
|
