URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [example/] [processor_check/] [main.c] - Diff between revs 70 and 71

Rev 70	Rev 71
Line 560...	Line 560...
`neorv32_cpu_csr_write(CSR_MCAUSE, 0);`	`neorv32_cpu_csr_write(CSR_MCAUSE, 0);`
`PRINT_STANDARD("[%i] I_ILLEG (illegal instr.) EXC: ", cnt_test);`	`PRINT_STANDARD("[%i] I_ILLEG (illegal instr.) EXC: ", cnt_test);`

`cnt_test++;`	`cnt_test++;`

`// illegal 32-bit instruction (malformed SUB)`	`// illegal 32-bit instruction (malformed SRA)`
`asm volatile (".align 4 \n"`	`asm volatile (".align 4 \n"`
`".word 0x80000033");`	`".word 0xC0000033");`

`// make sure this has cause an illegal exception`	`// make sure this has cause an illegal exception`
`if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {`	`if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {`
`// make sure this is really the instruction that caused the exception`	`// make sure this is really the instruction that caused the exception`
`// -> for illegal instructions MTVAL contains the faulting instruction word`	`// -> for illegal instructions MTVAL contains the faulting instruction word`
`if (neorv32_cpu_csr_read(CSR_MTVAL) == 0x80000033) {`	`if (neorv32_cpu_csr_read(CSR_MTVAL) == 0xC0000033) {`
`test_ok();`	`test_ok();`
`}`	`}`
`else {`	`else {`
`test_fail();`	`test_fail();`
`}`	`}`