| Line 382... |
Line 382... |
};
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};
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/**@}*/
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/**@}*/
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/**********************************************************************//**
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/**********************************************************************//**
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* @name IO Device: Serial Peripheral Interface Master (SPI)
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* @name IO Device: Serial Peripheral Interface Controller (SPI)
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**************************************************************************/
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**************************************************************************/
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/**@{*/
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/**@{*/
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/** SPI control register (r/w) */
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/** SPI control register (r/w) */
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#define SPI_CT (*(IO_REG32 0xFFFFFFA8UL))
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#define SPI_CT (*(IO_REG32 0xFFFFFFA8UL))
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/** SPI receive/transmit data register (r/w) */
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/** SPI receive/transmit data register (r/w) */
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| Line 418... |
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};
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};
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/**@}*/
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/**@}*/
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/**********************************************************************//**
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/**********************************************************************//**
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* @name IO Device: Two-Wire Interface Master (TWI)
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* @name IO Device: Two-Wire Interface Controller (TWI)
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**************************************************************************/
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**************************************************************************/
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/**@{*/
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/**@{*/
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/** TWI control register (r/w) */
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/** TWI control register (r/w) */
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#define TWI_CT (*(IO_REG32 0xFFFFFFB0UL))
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#define TWI_CT (*(IO_REG32 0xFFFFFFB0UL))
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/** TWI receive/transmit data register (r/w) */
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/** TWI receive/transmit data register (r/w) */
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| Line 435... |
Line 435... |
TWI_CT_STOP = 2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */
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TWI_CT_STOP = 2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */
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TWI_CT_IRQ_EN = 3, /**< TWI control register(3) (r/w): Enable transmission done interrupt */
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TWI_CT_IRQ_EN = 3, /**< TWI control register(3) (r/w): Enable transmission done interrupt */
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TWI_CT_PRSC0 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 0 */
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TWI_CT_PRSC0 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 0 */
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TWI_CT_PRSC1 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 1 */
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TWI_CT_PRSC1 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 1 */
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TWI_CT_PRSC2 = 6, /**< TWI control register(6) (r/w): Clock prescaler select bit 2 */
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TWI_CT_PRSC2 = 6, /**< TWI control register(6) (r/w): Clock prescaler select bit 2 */
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TWI_CT_MACK = 7, /**< TWI control register(7) (r/w): Generate master ACK for each transmission */
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TWI_CT_MACK = 7, /**< TWI control register(7) (r/w): Generate controller ACK for each transmission */
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TWI_CT_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */
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TWI_CT_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */
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TWI_CT_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
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TWI_CT_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
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};
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};
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