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Line 79... |
CSR_PMPADDR6 = 0x3b6, /**< 0x3b6 - pmpaddr6 (r/w): Physical memory protection address register 6 */
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CSR_PMPADDR6 = 0x3b6, /**< 0x3b6 - pmpaddr6 (r/w): Physical memory protection address register 6 */
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CSR_PMPADDR7 = 0x3b7, /**< 0x3b7 - pmpaddr7 (r/w): Physical memory protection address register 7 */
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CSR_PMPADDR7 = 0x3b7, /**< 0x3b7 - pmpaddr7 (r/w): Physical memory protection address register 7 */
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CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
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CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
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CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
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CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
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CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word - only 20-bit wide!*/
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CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word - only 20-bit wide!*/
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CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word - only 20-bit wide! */
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CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word - only 20-bit wide! */
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CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */
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CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */
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CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME_LO) */
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CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME_LO) */
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#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL))
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#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL))
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/**@}*/
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/**@}*/
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/**********************************************************************//**
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/**********************************************************************//**
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* @name IO Device: Dummy Device (DEVNULL)
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**************************************************************************/
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/**@{*/
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/** DEVNULL data register (r/w) */
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#define DEVNULL_DATA (*(IO_REG32 0xFFFFFF88UL))
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/**@}*/
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/**********************************************************************//**
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* @name IO Device: Watchdog Timer (WDT)
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* @name IO Device: Watchdog Timer (WDT)
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**************************************************************************/
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**************************************************************************/
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/**@{*/
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/**@{*/
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/** Watchdog control register (r/w) */
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/** Watchdog control register (r/w) */
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#define WDT_CT (*(IO_REG32 0xFFFFFF8CUL))
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#define WDT_CT (*(IO_REG32 0xFFFFFF8CUL))
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Line 463... |
};
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};
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/**@}*/
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/**@}*/
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/**********************************************************************//**
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/**********************************************************************//**
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* @name IO Device: Dummy Device (DEVNULL)
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**************************************************************************/
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/**@{*/
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/** DEVNULL data register (r/w) */
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#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFC8UL))
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/**@}*/
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/**********************************************************************//**
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* @name IO Device: System Configuration Info Memory (SYSINFO)
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* @name IO Device: System Configuration Info Memory (SYSINFO)
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**************************************************************************/
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**************************************************************************/
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/**@{*/
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/**@{*/
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/** SYSINFO(0): Clock speed */
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/** SYSINFO(0): Clock speed */
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#define SYSINFO_CLK (*(IO_ROM32 0xFFFFFFE0UL))
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#define SYSINFO_CLK (*(IO_ROM32 0xFFFFFFE0UL))
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