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CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) - only 20-bit wide! */
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CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) - only 20-bit wide! */
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CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
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CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
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CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
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CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
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CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
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CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
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CSR_MHARTID = 0xf14 /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
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CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
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CSR_MZEXT = 0xfc0 /**< 0xfc0 - mzext (custom CSR) (r/-): Available Z* CPU extensions */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
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* CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
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/**********************************************************************//**
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/**********************************************************************//**
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* @name Address space sections
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* @name Address space sections
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**************************************************************************/
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**************************************************************************/
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/**@{*/
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/**@{*/
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/** instruction memory base address (r/w/x) */
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/** instruction memory base address (r/w/x) */
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// -> use value from MEM_ISPACE_BASE CSR
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// -> use value from MEM_ISPACE_BASE generic
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/** data memory base address (r/w/x) */
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/** data memory base address (r/w/x) */
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// -> use value from MEM_DSPACE_BASE CSR
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// -> use value from MEM_DSPACE_BASE generic
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/** bootloader memory base address (r/-/x) */
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/** bootloader memory base address (r/-/x) */
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#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
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#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
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/** peripheral/IO devices memory base address (r/w/x) */
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/** peripheral/IO devices memory base address (r/w/x) */
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#define IO_BASE_ADDRESS (0xFFFFFF80UL)
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#define IO_BASE_ADDRESS (0xFFFFFF80UL)
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/**@}*/
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/**@}*/
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/**********************************************************************//**
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/**********************************************************************//**
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* @name IO Device: General Purpose Input/Output Port Unit (GPIO)
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* @name IO Device: General Purpose Input/Output Port Unit (GPIO)
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**************************************************************************/
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**************************************************************************/
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/**@{*/
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/**@{*/
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/** GPIO parallel input port (r/-) */
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/** GPIO parallel input port 32-bit (r/-) */
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#define GPIO_INPUT (*(IO_ROM32 0xFFFFFF80UL))
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#define GPIO_INPUT (*(IO_ROM32 0xFFFFFF80UL))
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/** GPIO parallel output port (r/w) */
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/** GPIO parallel output port 32-bit (r/w) */
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#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL))
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#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL))
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/**@}*/
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/**@}*/
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/**********************************************************************//**
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/**********************************************************************//**
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