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Rev 35 |
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TWI_CT_IRQ_EN = 3, /**< TWI control register(3) (r/w): Enable transmission done interrupt */
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TWI_CT_IRQ_EN = 3, /**< TWI control register(3) (r/w): Enable transmission done interrupt */
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TWI_CT_PRSC0 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 0 */
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TWI_CT_PRSC0 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 0 */
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TWI_CT_PRSC1 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 1 */
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TWI_CT_PRSC1 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 1 */
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TWI_CT_PRSC2 = 6, /**< TWI control register(6) (r/w): Clock prescaler select bit 2 */
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TWI_CT_PRSC2 = 6, /**< TWI control register(6) (r/w): Clock prescaler select bit 2 */
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TWI_CT_MACK = 7, /**< TWI control register(7) (r/w): Generate controller ACK for each transmission */
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TWI_CT_MACK = 7, /**< TWI control register(7) (r/w): Generate controller ACK for each transmission */
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TWI_CT_CKSTEN = 8, /**< TWI control register(8) (r/w): Enable clock stretching (by peripheral) */
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TWI_CT_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */
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TWI_CT_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */
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TWI_CT_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
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TWI_CT_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
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};
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};
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