| Line 55... |
Line 55... |
enum NEORV32_CPU_CSRS_enum {
|
enum NEORV32_CPU_CSRS_enum {
|
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */
|
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */
|
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */
|
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */
|
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */
|
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */
|
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */
|
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */
|
|
CSR_MCOUNTEREN = 0x306, /**< 0x305 - mcounteren (r/w): Machine counter enable register (controls access rights from U-mode) */
|
CSR_MSTATUSH = 0x310, /**< 0x310 - mstatush (r/-): Machine status register - high word */
|
CSR_MSTATUSH = 0x310, /**< 0x310 - mstatush (r/-): Machine status register - high word */
|
|
|
|
CSR_MCOUNTINHIBIT = 0x320, /**< 0x320 - mcountinhibit (r/w): Machine counter-inhibit register */
|
|
|
CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
|
CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
|
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */
|
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */
|
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */
|
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */
|
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */
|
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */
|
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */
|
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */
|
| Line 103... |
Line 106... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
|
* CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
|
**************************************************************************/
|
**************************************************************************/
|
enum NEORV32_CPU_MSTATUS_enum {
|
enum NEORV32_CPU_MSTATUS_enum {
|
CPU_MSTATUS_MIE = 3, /**< CPU mstatus CSR (3): MIE - Machine interrupt enable bit (r/w) */
|
CPU_MSTATUS_MIE = 3, /**< CPU mstatus CSR (3): MIE - Machine interrupt enable bit (r/w) */
|
|
CPU_MSTATUS_UBE = 6, /**< CPU mstatus CSR (6): UBE - User-mode endianness (little-endian=0, big-endian=1) (r/-) */
|
CPU_MSTATUS_MPIE = 7, /**< CPU mstatus CSR (7): MPIE - Machine previous interrupt enable bit (r/w) */
|
CPU_MSTATUS_MPIE = 7, /**< CPU mstatus CSR (7): MPIE - Machine previous interrupt enable bit (r/w) */
|
CPU_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) */
|
CPU_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) */
|
CPU_MSTATUS_MPP_H = 12 /**< CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) */
|
CPU_MSTATUS_MPP_H = 12 /**< CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) */
|
};
|
};
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* CPU <b>mstatush</b> CSR (r/-): Machine status - high word(RISC-V spec.)
|
* CPU <b>mstatush</b> CSR (r/-): Machine status - high word(RISC-V spec.)
|
**************************************************************************/
|
**************************************************************************/
|
enum NEORV32_CPU_MSTATUSH_enum {
|
enum NEORV32_CPU_MSTATUSH_enum {
|
CPU_MSTATUSH_MBE = 5 /**< CPU mstatush CSR (5): MBE - Machine endianness (little-endian=0, big-endian=1) (r/w) */
|
CPU_MSTATUSH_MBE = 5 /**< CPU mstatush CSR (5): MBE - Machine-mode endianness (little-endian=0, big-endian=1) (r/-) */
|
|
};
|
|
|
|
|
|
/**********************************************************************//**
|
|
* CPU <b>mcounteren</b> CSR (r/w): Machine counter enable (RISC-V spec.)
|
|
**************************************************************************/
|
|
enum NEORV32_CPU_MCOUNTEREN_enum {
|
|
CPU_MCOUNTEREN_CY = 0, /**< CPU mcounteren CSR (0): CY - Allow access to cycle[h] CSRs from U-mode when set (r/w) */
|
|
CPU_MCOUNTEREN_TM = 1, /**< CPU mcounteren CSR (1): TM - Allow access to time[h] CSRs from U-mode when set (r/w) */
|
|
CPU_MCOUNTEREN_IR = 2 /**< CPU mcounteren CSR (2): IR - Allow access to instret[h] CSRs from U-mode when set (r/w) */
|
|
};
|
|
|
|
|
|
/**********************************************************************//**
|
|
* CPU <b>mcountinhibit</b> CSR (r/w): Machine counter-inhibit (RISC-V spec.)
|
|
**************************************************************************/
|
|
enum NEORV32_CPU_MCOUNTINHIBIT_enum {
|
|
CPU_MCOUNTINHIBIT_CY = 0, /**< CPU mcountinhibit CSR (0): CY - Enable auto-increment of [m]cycle[h] CSR when set (r/w) */
|
|
CPU_MCOUNTINHIBIT_IR = 2 /**< CPU mcountinhibit CSR (2): IR - Enable auto-increment of [m]instret[h] CSR when set (r/w) */
|
};
|
};
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.)
|
* CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.)
|
| Line 170... |
Line 193... |
* CPU <b>mzext</b> custom CSR (r/-): Implemented Z* CPU extensions
|
* CPU <b>mzext</b> custom CSR (r/-): Implemented Z* CPU extensions
|
**************************************************************************/
|
**************************************************************************/
|
enum NEORV32_CPU_MZEXT_enum {
|
enum NEORV32_CPU_MZEXT_enum {
|
CPU_MZEXT_ZICSR = 0, /**< CPU mzext CSR (0): Zicsr extension available when set (r/-) */
|
CPU_MZEXT_ZICSR = 0, /**< CPU mzext CSR (0): Zicsr extension available when set (r/-) */
|
CPU_MZEXT_ZIFENCEI = 1, /**< CPU mzext CSR (1): Zifencei extension available when set (r/-) */
|
CPU_MZEXT_ZIFENCEI = 1, /**< CPU mzext CSR (1): Zifencei extension available when set (r/-) */
|
CPU_MZEXT_PMP = 2, /**< CPU mzext CSR (2): PMP extension available when set (r/-) */
|
CPU_MZEXT_PMP = 2 /**< CPU mzext CSR (2): PMP extension available when set (r/-) */
|
CPU_MZEXT_ZICNT = 3 /**< CPU mzext CSR (3): Standard RISC-V performance counters ([m]cycle[h] & [m]instret[h]) available when set (r/-) */
|
|
};
|
};
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* Trap codes from mcause CSR.
|
* Trap codes from mcause CSR.
|
| Line 519... |
Line 541... |
#define SYSINFO_CLK (*(IO_ROM32 0xFFFFFFE0UL))
|
#define SYSINFO_CLK (*(IO_ROM32 0xFFFFFFE0UL))
|
/** SYSINFO(1): Custom user code (via "USER_CODE" generic) */
|
/** SYSINFO(1): Custom user code (via "USER_CODE" generic) */
|
#define SYSINFO_USER_CODE (*(IO_ROM32 0xFFFFFFE4UL))
|
#define SYSINFO_USER_CODE (*(IO_ROM32 0xFFFFFFE4UL))
|
/** SYSINFO(2): Clock speed */
|
/** SYSINFO(2): Clock speed */
|
#define SYSINFO_FEATURES (*(IO_ROM32 0xFFFFFFE8UL))
|
#define SYSINFO_FEATURES (*(IO_ROM32 0xFFFFFFE8UL))
|
/** SYSINFO(3): reserved */
|
/** SYSINFO(3): Cache configuration */
|
#define SYSINFO_reserved (*(IO_ROM32 0xFFFFFFECUL))
|
#define SYSINFO_CACHE (*(IO_ROM32 0xFFFFFFECUL))
|
/** SYSINFO(4): Instruction memory address space base */
|
/** SYSINFO(4): Instruction memory address space base */
|
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 0xFFFFFFF0UL))
|
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 0xFFFFFFF0UL))
|
/** SYSINFO(5): Data memory address space base */
|
/** SYSINFO(5): Data memory address space base */
|
#define SYSINFO_DSPACE_BASE (*(IO_ROM32 0xFFFFFFF4UL))
|
#define SYSINFO_DSPACE_BASE (*(IO_ROM32 0xFFFFFFF4UL))
|
/** SYSINFO(6): Internal instruction memory (IMEM) size in bytes */
|
/** SYSINFO(6): Internal instruction memory (IMEM) size in bytes */
|
#define SYSINFO_IMEM_SIZE (*(IO_ROM32 0xFFFFFFF8UL))
|
#define SYSINFO_IMEM_SIZE (*(IO_ROM32 0xFFFFFFF8UL))
|
/** SYSINFO(7): Internal data memory (DMEM) size in bytes */
|
/** SYSINFO(7): Internal data memory (DMEM) size in bytes */
|
#define SYSINFO_DMEM_SIZE (*(IO_ROM32 0xFFFFFFFCUL))
|
#define SYSINFO_DMEM_SIZE (*(IO_ROM32 0xFFFFFFFCUL))
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* SYSINFO_FEATURES (r/-): Implemented processor devices/features
|
* SYSINFO_FEATURES (r/-): Implemented processor devices/features
|
**************************************************************************/
|
**************************************************************************/
|
enum NEORV32_SYSINFO_FEATURES_enum {
|
enum NEORV32_SYSINFO_FEATURES_enum {
|
SYSINFO_FEATURES_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_USE generic) */
|
SYSINFO_FEATURES_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_USE generic) */
|
SYSINFO_FEATURES_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_USE generic) */
|
SYSINFO_FEATURES_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_USE generic) */
|
SYSINFO_FEATURES_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */
|
SYSINFO_FEATURES_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */
|
SYSINFO_FEATURES_MEM_INT_IMEM_ROM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
|
SYSINFO_FEATURES_MEM_INT_IMEM_ROM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
|
SYSINFO_FEATURES_MEM_INT_DMEM = 4, /**< SYSINFO_FEATURES (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */
|
SYSINFO_FEATURES_MEM_INT_DMEM = 4, /**< SYSINFO_FEATURES (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */
|
SYSINFO_FEATURES_MEM_EXT_ENDIAN = 5, /**< SYSINFO_FEATURES (5) (r/-): External bus interface uses BIG-endian byte-order when 1 (via package.xbus_big_endian_c constant) */
|
SYSINFO_FEATURES_MEM_EXT_ENDIAN = 5, /**< SYSINFO_FEATURES (5) (r/-): External bus interface uses BIG-endian byte-order when 1 (via package.xbus_big_endian_c constant) */
|
|
SYSINFO_FEATURES_ICACHE = 6, /**< SYSINFO_FEATURES (6) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_USE generic) */
|
|
|
SYSINFO_FEATURES_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */
|
SYSINFO_FEATURES_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */
|
SYSINFO_FEATURES_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */
|
SYSINFO_FEATURES_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */
|
SYSINFO_FEATURES_IO_UART = 18, /**< SYSINFO_FEATURES (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_USE generic) */
|
SYSINFO_FEATURES_IO_UART = 18, /**< SYSINFO_FEATURES (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_USE generic) */
|
SYSINFO_FEATURES_IO_SPI = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_USE generic) */
|
SYSINFO_FEATURES_IO_SPI = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_USE generic) */
|
| Line 555... |
Line 577... |
SYSINFO_FEATURES_IO_CFU0 = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions unit 0 implemented when 1 (via IO_CFU0_USE generic) */
|
SYSINFO_FEATURES_IO_CFU0 = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions unit 0 implemented when 1 (via IO_CFU0_USE generic) */
|
SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
|
SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
|
SYSINFO_FEATURES_IO_CFU1 = 25 /**< SYSINFO_FEATURES (25) (r/-): Custom functions unit 1 implemented when 1 (via IO_CFU1_USE generic) */
|
SYSINFO_FEATURES_IO_CFU1 = 25 /**< SYSINFO_FEATURES (25) (r/-): Custom functions unit 1 implemented when 1 (via IO_CFU1_USE generic) */
|
};
|
};
|
|
|
|
/**********************************************************************//**
|
|
* SYSINFO_CACHE (r/-): Cache configuration
|
|
**************************************************************************/
|
|
enum NEORV32_SYSINFO_CACHE_enum {
|
|
SYSINFO_CACHE_IC_BLOCK_SIZE_0 = 0, /**< SYSINFO_CACHE (0) (r/-): i-cache: log2(Block size in bytes), bit 0 (via ICACHE_BLOCK_SIZE generic) */
|
|
SYSINFO_CACHE_IC_BLOCK_SIZE_1 = 1, /**< SYSINFO_CACHE (1) (r/-): i-cache: log2(Block size in bytes), bit 1 (via ICACHE_BLOCK_SIZE generic) */
|
|
SYSINFO_CACHE_IC_BLOCK_SIZE_2 = 2, /**< SYSINFO_CACHE (2) (r/-): i-cache: log2(Block size in bytes), bit 2 (via ICACHE_BLOCK_SIZE generic) */
|
|
SYSINFO_CACHE_IC_BLOCK_SIZE_3 = 3, /**< SYSINFO_CACHE (3) (r/-): i-cache: log2(Block size in bytes), bit 3 (via ICACHE_BLOCK_SIZE generic) */
|
|
|
|
SYSINFO_CACHE_IC_NUM_BLOCKS_0 = 4, /**< SYSINFO_CACHE (4) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 0 (via ICACHE_NUM_BLOCKS generic) */
|
|
SYSINFO_CACHE_IC_NUM_BLOCKS_1 = 5, /**< SYSINFO_CACHE (5) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 1 (via ICACHE_NUM_BLOCKS generic) */
|
|
SYSINFO_CACHE_IC_NUM_BLOCKS_2 = 6, /**< SYSINFO_CACHE (6) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 2 (via ICACHE_NUM_BLOCKS generic) */
|
|
SYSINFO_CACHE_IC_NUM_BLOCKS_3 = 7, /**< SYSINFO_CACHE (7) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 3 (via ICACHE_NUM_BLOCKS generic) */
|
|
|
|
SYSINFO_CACHE_IC_ASSOCIATIVITY_0 = 8, /**< SYSINFO_CACHE (10) (r/-): i-cache: log2(associativity), bit 0 (always 0 -> direct mapped) */
|
|
SYSINFO_CACHE_IC_ASSOCIATIVITY_1 = 9, /**< SYSINFO_CACHE (11) (r/-): i-cache: log2(associativity), bit 1 (always 0 -> direct mapped) */
|
|
SYSINFO_CACHE_IC_ASSOCIATIVITY_2 = 10, /**< SYSINFO_CACHE (12) (r/-): i-cache: log2(associativity), bit 2 (always 0 -> direct mapped) */
|
|
SYSINFO_CACHE_IC_ASSOCIATIVITY_3 = 11, /**< SYSINFO_CACHE (13) (r/-): i-cache: log2(associativity), bit 3 (always 0 -> direct mapped) */
|
|
};
|
|
|
|
|
// ----------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------
|
// Include all IO driver headers
|
// Include all IO driver headers
|
// ----------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------
|
// cpu core
|
// cpu core
|
