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Line 438... |
* CPU <b>mzext</b> custom CSR (r/-): Implemented Z* CPU extensions
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* CPU <b>mzext</b> custom CSR (r/-): Implemented Z* CPU extensions
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**************************************************************************/
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**************************************************************************/
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enum NEORV32_CSR_MZEXT_enum {
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enum NEORV32_CSR_MZEXT_enum {
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CSR_MZEXT_ZICSR = 0, /**< CPU mzext CSR (0): Zicsr extension available when set (r/-) */
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CSR_MZEXT_ZICSR = 0, /**< CPU mzext CSR (0): Zicsr extension available when set (r/-) */
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CSR_MZEXT_ZIFENCEI = 1, /**< CPU mzext CSR (1): Zifencei extension available when set (r/-) */
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CSR_MZEXT_ZIFENCEI = 1, /**< CPU mzext CSR (1): Zifencei extension available when set (r/-) */
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CSR_MZEXT_ZBB = 2 /**< CPU mzext CSR (2): Zbb extension available when set (r/-) */
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CSR_MZEXT_ZBB = 2, /**< CPU mzext CSR (2): Zbb extension available when set (r/-) */
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CSR_MZEXT_ZBS = 3 /**< CPU mzext CSR (3): Zbs extension available when set (r/-) */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* CPU <b>mhpmevent</b> hardware performance monitor events
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* CPU <b>mhpmevent</b> hardware performance monitor events
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Line 734... |
UART_CT_BAUD07 = 7, /**< UART control register(7) (r/w): BAUD rate config value (12-bit, bit 6) */
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UART_CT_BAUD07 = 7, /**< UART control register(7) (r/w): BAUD rate config value (12-bit, bit 6) */
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UART_CT_BAUD08 = 8, /**< UART control register(8) (r/w): BAUD rate config value (12-bit, bit 7) */
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UART_CT_BAUD08 = 8, /**< UART control register(8) (r/w): BAUD rate config value (12-bit, bit 7) */
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UART_CT_BAUD09 = 9, /**< UART control register(9) (r/w): BAUD rate config value (12-bit, bit 8) */
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UART_CT_BAUD09 = 9, /**< UART control register(9) (r/w): BAUD rate config value (12-bit, bit 8) */
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UART_CT_BAUD10 = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bit, bit 9) */
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UART_CT_BAUD10 = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bit, bit 9) */
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UART_CT_BAUD11 = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bit, bit 0) */
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UART_CT_BAUD11 = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bit, bit 0) */
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UART_CT_SIM_MODE = 12, /**< UART control register(12) (r/w): Simulation output override enable, for use in simulation only */
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UART_CT_SIM_MODE = 12, /**< UART control register(12) (r/w): Simulation output override enable, for use in simulation only */
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UART_CT_RTS_EN = 20, /**< UART control register(20) (r/w): Enable hardware flow control: Assert RTS output if UART.RX is ready to receive */
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UART_CT_CTS_EN = 21, /**< UART control register(21) (r/w): Enable hardware flow control: UART.TX starts sending only if CTS input is asserted */
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UART_CT_PMODE0 = 22, /**< UART control register(22) (r/w): Parity configuration (0=even; 1=odd) */
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UART_CT_PMODE0 = 22, /**< UART control register(22) (r/w): Parity configuration (0=even; 1=odd) */
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UART_CT_PMODE1 = 23, /**< UART control register(23) (r/w): Parity bit enabled when set */
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UART_CT_PMODE1 = 23, /**< UART control register(23) (r/w): Parity bit enabled when set */
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UART_CT_PRSC0 = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
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UART_CT_PRSC0 = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
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UART_CT_PRSC1 = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
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UART_CT_PRSC1 = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
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UART_CT_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
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UART_CT_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
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UART_CT_CTS = 27, /**< UART control register(27) (r/-): current state of CTS input */
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UART_CT_EN = 28, /**< UART control register(28) (r/w): UART global enable */
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UART_CT_EN = 28, /**< UART control register(28) (r/w): UART global enable */
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UART_CT_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */
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UART_CT_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */
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};
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};
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/** UART0/UART1 parity configuration */
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enum NEORV32_UART_PARITY_enum {
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PARITY_NONE = 0b00, /**< 0b00: No parity bit at all */
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PARITY_EVEN = 0b10, /**< 0b10: Even parity */
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PARITY_ODD = 0b11 /**< 0b11: Odd parity */
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};
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/** UART0/UART1 hardware flow control configuration */
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enum NEORV32_UART_FLOW_CONTROL_enum {
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FLOW_CONTROL_NONE = 0b00, /**< 0b00: No hardware flow control */
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FLOW_CONTROL_RTS = 0b01, /**< 0b01: Assert RTS output if UART.RX is ready to receive */
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FLOW_CONTROL_CTS = 0b10, /**< 0b10: UART.TX starts sending only if CTS input is asserted */
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FLOW_CONTROL_RTSCTS = 0b11 /**< 0b11: Assert RTS output if UART.RX is ready to receive & UART.TX starts sending only if CTS input is asserted */
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};
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/** UART0/UART1 receive/transmit data register bits */
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/** UART0/UART1 receive/transmit data register bits */
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enum NEORV32_UART_DATA_enum {
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enum NEORV32_UART_DATA_enum {
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UART_DATA_LSB = 0, /**< UART receive/transmit data register(0) (r/w): Receive/transmit data LSB (bit 0) */
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UART_DATA_LSB = 0, /**< UART receive/transmit data register(0) (r/w): Receive/transmit data LSB (bit 0) */
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UART_DATA_MSB = 7, /**< UART receive/transmit data register(7) (r/w): Receive/transmit data MSB (bit 7) */
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UART_DATA_MSB = 7, /**< UART receive/transmit data register(7) (r/w): Receive/transmit data MSB (bit 7) */
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| Line 778... |
Line 796... |
SPI_CT_CS3 = 3, /**< UART control register(3) (r/w): Direct chip select line 3 (output is low when set) */
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SPI_CT_CS3 = 3, /**< UART control register(3) (r/w): Direct chip select line 3 (output is low when set) */
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SPI_CT_CS4 = 4, /**< UART control register(4) (r/w): Direct chip select line 4 (output is low when set) */
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SPI_CT_CS4 = 4, /**< UART control register(4) (r/w): Direct chip select line 4 (output is low when set) */
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SPI_CT_CS5 = 5, /**< UART control register(5) (r/w): Direct chip select line 5 (output is low when set) */
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SPI_CT_CS5 = 5, /**< UART control register(5) (r/w): Direct chip select line 5 (output is low when set) */
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SPI_CT_CS6 = 6, /**< UART control register(6) (r/w): Direct chip select line 6 (output is low when set) */
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SPI_CT_CS6 = 6, /**< UART control register(6) (r/w): Direct chip select line 6 (output is low when set) */
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SPI_CT_CS7 = 7, /**< UART control register(7) (r/w): Direct chip select line 7 (output is low when set) */
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SPI_CT_CS7 = 7, /**< UART control register(7) (r/w): Direct chip select line 7 (output is low when set) */
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SPI_CT_EN = 8, /**< UART control register(8) (r/w): SPI unit enable */
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SPI_CT_EN = 8, /**< UART control register(8) (r/w): SPI unit enable */
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SPI_CT_CPHA = 9, /**< UART control register(9) (r/w): Clock polarity (idle polarity) */
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SPI_CT_CPHA = 9, /**< UART control register(9) (r/w): Clock polarity (idle polarity) */
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SPI_CT_PRSC0 = 10, /**< UART control register(10) (r/w): Clock prescaler select bit 0 */
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SPI_CT_PRSC0 = 10, /**< UART control register(10) (r/w): Clock prescaler select bit 0 */
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SPI_CT_PRSC1 = 11, /**< UART control register(11) (r/w): Clock prescaler select bit 1 */
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SPI_CT_PRSC1 = 11, /**< UART control register(11) (r/w): Clock prescaler select bit 1 */
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SPI_CT_PRSC2 = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */
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SPI_CT_PRSC2 = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */
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