| Line 125... |
Line 125... |
CPU_MIP_MEIP = 11 /**< CPU mip CSR (11): Machine external interrupt (via CLIC) pending (r/-) */
|
CPU_MIP_MEIP = 11 /**< CPU mip CSR (11): Machine external interrupt (via CLIC) pending (r/-) */
|
};
|
};
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
|
* CPU <b>misa</b> CSR (r/w): Machine instruction set extensions (RISC-V spec.)
|
|
**************************************************************************/
|
|
enum NEORV32_CPU_MISA_enum {
|
|
CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/w), can be switched on/off */
|
|
CPU_MISA_E_EXT = 4, /**< CPU misa CSR (3): E: Embedded CPU extension available (r/-) */
|
|
CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
|
|
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/w), can be switched on/off */
|
|
CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
|
|
CPU_MISA_Z_EXT = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension available (r/-) */
|
|
CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
|
|
CPU_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
|
|
};
|
|
|
|
|
|
/**********************************************************************//**
|
* CPU <b>mfeatures</b> CSR (r/-): Implemented processor devices/features (CUSTOM)
|
* CPU <b>mfeatures</b> CSR (r/-): Implemented processor devices/features (CUSTOM)
|
**************************************************************************/
|
**************************************************************************/
|
enum NEORV32_CPU_MFEATURES_enum {
|
enum NEORV32_CPU_MFEATURES_enum {
|
CPU_MFEATURES_BOOTLOADER = 0, /**< CPU mfeatures CSR (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_USE generic) */
|
CPU_MFEATURES_BOOTLOADER = 0, /**< CPU mfeatures CSR (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_USE generic) */
|
CPU_MFEATURES_MEM_EXT = 1, /**< CPU mfeatures CSR (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_USE generic) */
|
CPU_MFEATURES_MEM_EXT = 1, /**< CPU mfeatures CSR (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_USE generic) */
|
CPU_MFEATURES_MEM_INT_IMEM = 2, /**< CPU mfeatures CSR (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */
|
CPU_MFEATURES_MEM_INT_IMEM = 2, /**< CPU mfeatures CSR (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */
|
CPU_MFEATURES_MEM_INT_IMEM_ROM = 3, /**< CPU mfeatures CSR (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
|
CPU_MFEATURES_MEM_INT_IMEM_ROM = 3, /**< CPU mfeatures CSR (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
|
CPU_MFEATURES_MEM_INT_DMEM = 4, /**< CPU mfeatures CSR (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */
|
CPU_MFEATURES_MEM_INT_DMEM = 4, /**< CPU mfeatures CSR (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */
|
|
CPU_MFEATURES_CSR_COUNTERS = 5, /**< CPU mfeatures CSR (5) (r/-): RISC-V performance counters implemented when 1 (via CSR_COUNTERS_USE generic) */
|
|
|
CPU_MFEATURES_IO_GPIO = 16, /**< CPU mfeatures CSR (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */
|
CPU_MFEATURES_IO_GPIO = 16, /**< CPU mfeatures CSR (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */
|
CPU_MFEATURES_IO_MTIME = 17, /**< CPU mfeatures CSR (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */
|
CPU_MFEATURES_IO_MTIME = 17, /**< CPU mfeatures CSR (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */
|
CPU_MFEATURES_IO_UART = 18, /**< CPU mfeatures CSR (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_USE generic) */
|
CPU_MFEATURES_IO_UART = 18, /**< CPU mfeatures CSR (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_USE generic) */
|
CPU_MFEATURES_IO_SPI = 19, /**< CPU mfeatures CSR (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_USE generic) */
|
CPU_MFEATURES_IO_SPI = 19, /**< CPU mfeatures CSR (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_USE generic) */
|
| Line 209... |
Line 225... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name Address space sections
|
* @name Address space sections
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** instruction memory base address (r/w/x) */
|
/** instruction memory base address (r/w/x) */
|
#define INSTR_MEM_BASE_ADDR 0x00000000
|
// -> use value from MEM_ISPACE_BASE CSR
|
/** data memory base address (r/w/x) */
|
/** data memory base address (r/w/x) */
|
#define DATA_MEM_BASE_ADDR 0x80000000
|
// -> use value from MEM_DSPACE_BASE CSR
|
/** bootloader memory base address (r/-/x) */
|
/** bootloader memory base address (r/-/x) */
|
#define BOOTLOADER_BASE_ADDRESS 0xFFFF0000
|
#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
|
/** peripheral/IO devices memory base address (r/w/x) */
|
/** peripheral/IO devices memory base address (r/w/x) */
|
#define IO_BASE_ADDRESS 0xFFFFFF80
|
#define IO_BASE_ADDRESS (0xFFFFFF80UL)
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: General Purpose Input/Output Port Unit (GPIO)
|
* @name IO Device: General Purpose Input/Output Port Unit (GPIO)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** GPIO parallel input port (r/-) */
|
/** GPIO parallel input port (r/-) */
|
#define GPIO_INPUT (*(IO_ROM32 0xFFFFFF80))
|
#define GPIO_INPUT (*(IO_ROM32 0xFFFFFF80UL))
|
/** GPIO parallel output port (r/w) */
|
/** GPIO parallel output port (r/w) */
|
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84))
|
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL))
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Core Local Interrupts Controller (CLIC)
|
* @name IO Device: Core Local Interrupts Controller (CLIC)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** CLIC control register (r/w) */
|
/** CLIC control register (r/w) */
|
#define CLIC_CT (*(IO_REG32 0xFFFFFF88))
|
#define CLIC_CT (*(IO_REG32 0xFFFFFF88UL))
|
|
|
/** CLIC control register bits */
|
/** CLIC control register bits */
|
enum NEORV32_CLIC_CT_enum {
|
enum NEORV32_CLIC_CT_enum {
|
CLIC_CT_SRC0 = 0, /**< CLIC control register(0) (r/-): IRQ source bit 0 */
|
CLIC_CT_SRC0 = 0, /**< CLIC control register(0) (r/-): IRQ source bit 0 */
|
CLIC_CT_SRC1 = 1, /**< CLIC control register(1) (r/-): IRQ source bit 1 */
|
CLIC_CT_SRC1 = 1, /**< CLIC control register(1) (r/-): IRQ source bit 1 */
|
| Line 282... |
Line 298... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Watchdog Timer (WDT)
|
* @name IO Device: Watchdog Timer (WDT)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** Watchdog control register (r/w) */
|
/** Watchdog control register (r/w) */
|
#define WDT_CT (*(IO_REG32 0xFFFFFF8C))
|
#define WDT_CT (*(IO_REG32 0xFFFFFF8CUL))
|
|
|
/** WTD control register bits */
|
/** WTD control register bits */
|
enum NEORV32_WDT_CT_enum {
|
enum NEORV32_WDT_CT_enum {
|
WDT_CT_CLK_SEL0 = 0, /**< WDT control register(0) (r/w): Clock prescaler select bit 0 */
|
WDT_CT_CLK_SEL0 = 0, /**< WDT control register(0) (r/w): Clock prescaler select bit 0 */
|
WDT_CT_CLK_SEL1 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 1 */
|
WDT_CT_CLK_SEL1 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 1 */
|
| Line 308... |
Line 324... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Machine System Timer (MTIME)
|
* @name IO Device: Machine System Timer (MTIME)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** MTIME (time register) low word (r/-) */
|
/** MTIME (time register) low word (r/-) */
|
#define MTIME_LO (*(IO_ROM32 0xFFFFFF90))
|
#define MTIME_LO (*(IO_ROM32 0xFFFFFF90UL))
|
/** MTIME (time register) high word (r/-) */
|
/** MTIME (time register) high word (r/-) */
|
#define MTIME_HI (*(IO_ROM32 0xFFFFFF94))
|
#define MTIME_HI (*(IO_ROM32 0xFFFFFF94UL))
|
/** MTIMECMP (time compare register) low word (r/w) */
|
/** MTIMECMP (time compare register) low word (r/w) */
|
#define MTIMECMP_LO (*(IO_REG32 0xFFFFFF98))
|
#define MTIMECMP_LO (*(IO_REG32 0xFFFFFF98UL))
|
/** MTIMECMP (time register) high word (r/w) */
|
/** MTIMECMP (time register) high word (r/w) */
|
#define MTIMECMP_HI (*(IO_REG32 0xFFFFFF9C))
|
#define MTIMECMP_HI (*(IO_REG32 0xFFFFFF9CUL))
|
|
|
/** MTIME (time register) 64-bit access (r/-) */
|
/** MTIME (time register) 64-bit access (r/-) */
|
#define MTIME (*(IO_ROM64 (&MTIME_LO)))
|
#define MTIME (*(IO_ROM64 (&MTIME_LO)))
|
/** MTIMECMP (time compare register) low word (r/w) */
|
/** MTIMECMP (time compare register) low word (r/w) */
|
#define MTIMECMP (*(IO_REG64 (&MTIMECMP_LO)))
|
#define MTIMECMP (*(IO_REG64 (&MTIMECMP_LO)))
|
| Line 328... |
Line 344... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Universal Asynchronous Receiver and Transmitter (UART)
|
* @name IO Device: Universal Asynchronous Receiver and Transmitter (UART)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** UART control register (r/w) */
|
/** UART control register (r/w) */
|
#define UART_CT (*(IO_REG32 0xFFFFFFA0))
|
#define UART_CT (*(IO_REG32 0xFFFFFFA0UL))
|
/** UART receive/transmit data register (r/w) */
|
/** UART receive/transmit data register (r/w) */
|
#define UART_DATA (*(IO_REG32 0xFFFFFFA4))
|
#define UART_DATA (*(IO_REG32 0xFFFFFFA4UL))
|
|
|
/** UART control register bits */
|
/** UART control register bits */
|
enum NEORV32_UART_CT_enum {
|
enum NEORV32_UART_CT_enum {
|
UART_CT_BAUD00 = 0, /**< UART control register(0) (r/w): BAUD rate config value lsb (12-bi, bit 0) */
|
UART_CT_BAUD00 = 0, /**< UART control register(0) (r/w): BAUD rate config value lsb (12-bi, bit 0) */
|
UART_CT_BAUD01 = 1, /**< UART control register(1) (r/w): BAUD rate config value (12-bi, bit 1) */
|
UART_CT_BAUD01 = 1, /**< UART control register(1) (r/w): BAUD rate config value (12-bi, bit 1) */
|
| Line 371... |
Line 387... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Serial Peripheral Interface Master (SPI)
|
* @name IO Device: Serial Peripheral Interface Master (SPI)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** SPI control register (r/w) */
|
/** SPI control register (r/w) */
|
#define SPI_CT (*(IO_REG32 0xFFFFFFA8))
|
#define SPI_CT (*(IO_REG32 0xFFFFFFA8UL))
|
/** SPI receive/transmit data register (r/w) */
|
/** SPI receive/transmit data register (r/w) */
|
#define SPI_DATA (*(IO_REG32 0xFFFFFFAC))
|
#define SPI_DATA (*(IO_REG32 0xFFFFFFACUL))
|
|
|
/** SPI control register bits */
|
/** SPI control register bits */
|
enum NEORV32_SPI_CT_enum {
|
enum NEORV32_SPI_CT_enum {
|
SPI_CT_CS0 = 0, /**< UART control register(0) (r/w): Direct chip select line 0 (output is low when set) */
|
SPI_CT_CS0 = 0, /**< UART control register(0) (r/w): Direct chip select line 0 (output is low when set) */
|
SPI_CT_CS1 = 1, /**< UART control register(1) (r/w): Direct chip select line 1 (output is low when set) */
|
SPI_CT_CS1 = 1, /**< UART control register(1) (r/w): Direct chip select line 1 (output is low when set) */
|
| Line 407... |
Line 423... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Two-Wire Interface Master (TWI)
|
* @name IO Device: Two-Wire Interface Master (TWI)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** TWI control register (r/w) */
|
/** TWI control register (r/w) */
|
#define TWI_CT (*(IO_REG32 0xFFFFFFB0))
|
#define TWI_CT (*(IO_REG32 0xFFFFFFB0UL))
|
/** TWI receive/transmit data register (r/w) */
|
/** TWI receive/transmit data register (r/w) */
|
#define TWI_DATA (*(IO_REG32 0xFFFFFFB4))
|
#define TWI_DATA (*(IO_REG32 0xFFFFFFB4UL))
|
|
|
/** TWI control register bits */
|
/** TWI control register bits */
|
enum NEORV32_TWI_CT_enum {
|
enum NEORV32_TWI_CT_enum {
|
TWI_CT_EN = 0, /**< TWI control register(0) (r/w): TWI enable */
|
TWI_CT_EN = 0, /**< TWI control register(0) (r/w): TWI enable */
|
TWI_CT_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
|
TWI_CT_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
|
| Line 439... |
Line 455... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Pulse Width Modulation Controller (PWM)
|
* @name IO Device: Pulse Width Modulation Controller (PWM)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** PWM control register (r/w) */
|
/** PWM control register (r/w) */
|
#define PWM_CT (*(IO_REG32 0xFFFFFFB8)) // r/w: control register
|
#define PWM_CT (*(IO_REG32 0xFFFFFFB8UL)) // r/w: control register
|
/** PWM duty cycle register (4-channels) (r/w) */
|
/** PWM duty cycle register (4-channels) (r/w) */
|
#define PWM_DUTY (*(IO_REG32 0xFFFFFFBC)) // r/w: duty cycle channel 1 and 0
|
#define PWM_DUTY (*(IO_REG32 0xFFFFFFBCUL)) // r/w: duty cycle channel 1 and 0
|
|
|
/** PWM control register bits */
|
/** PWM control register bits */
|
enum NEORV32_PWM_CT_enum {
|
enum NEORV32_PWM_CT_enum {
|
PWM_CT_EN = 0, /**< PWM control register(0) (r/w): PWM controller enable */
|
PWM_CT_EN = 0, /**< PWM control register(0) (r/w): PWM controller enable */
|
PWM_CT_PRSC0 = 1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
|
PWM_CT_PRSC0 = 1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
|
| Line 470... |
Line 486... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: True Random Number Generator (TRNG)
|
* @name IO Device: True Random Number Generator (TRNG)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** TRNG control register (r/w) */
|
/** TRNG control register (r/w) */
|
#define TRNG_CT (*(IO_REG32 0xFFFFFFC0))
|
#define TRNG_CT (*(IO_REG32 0xFFFFFFC0UL))
|
/** TRNG data register (r/-) */
|
/** TRNG data register (r/-) */
|
#define TRNG_DATA (*(IO_ROM32 0xFFFFFFC4))
|
#define TRNG_DATA (*(IO_ROM32 0xFFFFFFC4UL))
|
|
|
/** TRNG control register bits */
|
/** TRNG control register bits */
|
enum NEORV32_TRNG_CT_enum {
|
enum NEORV32_TRNG_CT_enum {
|
TRNG_CT_TAP_LSB = 0, /**< TRNG control register(0) (r/w): TAP mask (16-bit) LSB */
|
TRNG_CT_TAP_LSB = 0, /**< TRNG control register(0) (r/w): TAP mask (16-bit) LSB */
|
TRNG_CT_TAP_MSB = 15, /**< TRNG control register(15) (r/w): TAP mask (16-bit) MSB */
|
TRNG_CT_TAP_MSB = 15, /**< TRNG control register(15) (r/w): TAP mask (16-bit) MSB */
|
| Line 494... |
Line 510... |
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Dummy Device (DEVNULL)
|
* @name IO Device: Dummy Device (DEVNULL)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** TRNG data register (r/w) */
|
/** DEVNULL data register (r/w) */
|
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFFC))
|
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFFCUL))
|
/**@}*/
|
/**@}*/
|
|
|
|
|
// ----------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------
|
// Include all IO driver headers
|
// Include all IO driver headers
|
