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**************************************************************************/
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**************************************************************************/
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#ifndef neorv32_h
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#ifndef neorv32_h
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#define neorv32_h
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#define neorv32_h
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Standard libraries
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// Standard libraries
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#include <stdint.h>
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#include <stdint.h>
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#include <inttypes.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <limits.h>
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CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */
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CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */
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CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME_LO) */
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CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME_LO) */
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CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word (from MINSTRET) */
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CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word (from MINSTRET) */
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CSR_HPMCOUNTER3 = 0xc03, /**< 0xc03 - hpmcounter3 (r/w): Hardware performance monitor 3 counter low word */
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CSR_HPMCOUNTER4 = 0xc04, /**< 0xc04 - hpmcounter4 (r/w): Hardware performance monitor 4 counter low word */
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CSR_HPMCOUNTER5 = 0xc05, /**< 0xc05 - hpmcounter5 (r/w): Hardware performance monitor 5 counter low word */
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CSR_HPMCOUNTER6 = 0xc06, /**< 0xc06 - hpmcounter6 (r/w): Hardware performance monitor 6 counter low word */
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CSR_HPMCOUNTER7 = 0xc07, /**< 0xc07 - hpmcounter7 (r/w): Hardware performance monitor 7 counter low word */
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CSR_HPMCOUNTER8 = 0xc08, /**< 0xc08 - hpmcounter8 (r/w): Hardware performance monitor 8 counter low word */
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CSR_HPMCOUNTER9 = 0xc09, /**< 0xc09 - hpmcounter9 (r/w): Hardware performance monitor 9 counter low word */
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CSR_HPMCOUNTER10 = 0xc0a, /**< 0xc0a - hpmcounter10 (r/w): Hardware performance monitor 10 counter low word */
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CSR_HPMCOUNTER11 = 0xc0b, /**< 0xc0b - hpmcounter11 (r/w): Hardware performance monitor 11 counter low word */
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CSR_HPMCOUNTER12 = 0xc0c, /**< 0xc0c - hpmcounter12 (r/w): Hardware performance monitor 12 counter low word */
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CSR_HPMCOUNTER13 = 0xc0d, /**< 0xc0d - hpmcounter13 (r/w): Hardware performance monitor 13 counter low word */
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CSR_HPMCOUNTER14 = 0xc0e, /**< 0xc0e - hpmcounter14 (r/w): Hardware performance monitor 14 counter low word */
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CSR_HPMCOUNTER15 = 0xc0f, /**< 0xc0f - hpmcounter15 (r/w): Hardware performance monitor 15 counter low word */
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CSR_HPMCOUNTER16 = 0xc10, /**< 0xc10 - hpmcounter16 (r/w): Hardware performance monitor 16 counter low word */
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CSR_HPMCOUNTER17 = 0xc11, /**< 0xc11 - hpmcounter17 (r/w): Hardware performance monitor 17 counter low word */
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CSR_HPMCOUNTER18 = 0xc12, /**< 0xc12 - hpmcounter18 (r/w): Hardware performance monitor 18 counter low word */
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CSR_HPMCOUNTER19 = 0xc13, /**< 0xc13 - hpmcounter19 (r/w): Hardware performance monitor 19 counter low word */
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CSR_HPMCOUNTER20 = 0xc14, /**< 0xc14 - hpmcounter20 (r/w): Hardware performance monitor 20 counter low word */
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CSR_HPMCOUNTER21 = 0xc15, /**< 0xc15 - hpmcounter21 (r/w): Hardware performance monitor 21 counter low word */
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CSR_HPMCOUNTER22 = 0xc16, /**< 0xc16 - hpmcounter22 (r/w): Hardware performance monitor 22 counter low word */
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CSR_HPMCOUNTER23 = 0xc17, /**< 0xc17 - hpmcounter23 (r/w): Hardware performance monitor 23 counter low word */
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CSR_HPMCOUNTER24 = 0xc18, /**< 0xc18 - hpmcounter24 (r/w): Hardware performance monitor 24 counter low word */
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CSR_HPMCOUNTER25 = 0xc19, /**< 0xc19 - hpmcounter25 (r/w): Hardware performance monitor 25 counter low word */
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CSR_HPMCOUNTER26 = 0xc1a, /**< 0xc1a - hpmcounter26 (r/w): Hardware performance monitor 26 counter low word */
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CSR_HPMCOUNTER27 = 0xc1b, /**< 0xc1b - hpmcounter27 (r/w): Hardware performance monitor 27 counter low word */
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CSR_HPMCOUNTER28 = 0xc1c, /**< 0xc1c - hpmcounter28 (r/w): Hardware performance monitor 28 counter low word */
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CSR_HPMCOUNTER29 = 0xc1d, /**< 0xc1d - hpmcounter29 (r/w): Hardware performance monitor 29 counter low word */
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CSR_HPMCOUNTER30 = 0xc1e, /**< 0xc1e - hpmcounter30 (r/w): Hardware performance monitor 30 counter low word */
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CSR_HPMCOUNTER31 = 0xc1f, /**< 0xc1f - hpmcounter31 (r/w): Hardware performance monitor 31 counter low word */
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CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word (from MCYCLEH) */
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CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word (from MCYCLEH) */
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CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME_HI) */
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CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME_HI) */
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CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) */
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CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) */
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CSR_HPMCOUNTER3H = 0xc83, /**< 0xc83 - hpmcounter3h (r/w): Hardware performance monitor 3 counter high word */
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CSR_HPMCOUNTER4H = 0xc84, /**< 0xc84 - hpmcounter4h (r/w): Hardware performance monitor 4 counter high word */
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CSR_HPMCOUNTER5H = 0xc85, /**< 0xc85 - hpmcounter5h (r/w): Hardware performance monitor 5 counter high word */
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CSR_HPMCOUNTER6H = 0xc86, /**< 0xc86 - hpmcounter6h (r/w): Hardware performance monitor 6 counter high word */
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CSR_HPMCOUNTER7H = 0xc87, /**< 0xc87 - hpmcounter7h (r/w): Hardware performance monitor 7 counter high word */
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CSR_HPMCOUNTER8H = 0xc88, /**< 0xc88 - hpmcounter8h (r/w): Hardware performance monitor 8 counter high word */
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CSR_HPMCOUNTER9H = 0xc89, /**< 0xc89 - hpmcounter9h (r/w): Hardware performance monitor 9 counter high word */
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CSR_HPMCOUNTER10H = 0xc8a, /**< 0xc8a - hpmcounter10h (r/w): Hardware performance monitor 10 counter high word */
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CSR_HPMCOUNTER11H = 0xc8b, /**< 0xc8b - hpmcounter11h (r/w): Hardware performance monitor 11 counter high word */
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CSR_HPMCOUNTER12H = 0xc8c, /**< 0xc8c - hpmcounter12h (r/w): Hardware performance monitor 12 counter high word */
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CSR_HPMCOUNTER13H = 0xc8d, /**< 0xc8d - hpmcounter13h (r/w): Hardware performance monitor 13 counter high word */
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CSR_HPMCOUNTER14H = 0xc8e, /**< 0xc8e - hpmcounter14h (r/w): Hardware performance monitor 14 counter high word */
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CSR_HPMCOUNTER15H = 0xc8f, /**< 0xc8f - hpmcounter15h (r/w): Hardware performance monitor 15 counter high word */
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CSR_HPMCOUNTER16H = 0xc90, /**< 0xc90 - hpmcounter16h (r/w): Hardware performance monitor 16 counter high word */
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CSR_HPMCOUNTER17H = 0xc91, /**< 0xc91 - hpmcounter17h (r/w): Hardware performance monitor 17 counter high word */
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CSR_HPMCOUNTER18H = 0xc92, /**< 0xc92 - hpmcounter18h (r/w): Hardware performance monitor 18 counter high word */
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CSR_HPMCOUNTER19H = 0xc93, /**< 0xc93 - hpmcounter19h (r/w): Hardware performance monitor 19 counter high word */
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CSR_HPMCOUNTER20H = 0xc94, /**< 0xc94 - hpmcounter20h (r/w): Hardware performance monitor 20 counter high word */
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CSR_HPMCOUNTER21H = 0xc95, /**< 0xc95 - hpmcounter21h (r/w): Hardware performance monitor 21 counter high word */
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CSR_HPMCOUNTER22H = 0xc96, /**< 0xc96 - hpmcounter22h (r/w): Hardware performance monitor 22 counter high word */
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CSR_HPMCOUNTER23H = 0xc97, /**< 0xc97 - hpmcounter23h (r/w): Hardware performance monitor 23 counter high word */
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CSR_HPMCOUNTER24H = 0xc98, /**< 0xc98 - hpmcounter24h (r/w): Hardware performance monitor 24 counter high word */
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CSR_HPMCOUNTER25H = 0xc99, /**< 0xc99 - hpmcounter25h (r/w): Hardware performance monitor 25 counter high word */
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CSR_HPMCOUNTER26H = 0xc9a, /**< 0xc9a - hpmcounter26h (r/w): Hardware performance monitor 26 counter high word */
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CSR_HPMCOUNTER27H = 0xc9b, /**< 0xc9b - hpmcounter27h (r/w): Hardware performance monitor 27 counter high word */
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CSR_HPMCOUNTER28H = 0xc9c, /**< 0xc9c - hpmcounter28h (r/w): Hardware performance monitor 28 counter high word */
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CSR_HPMCOUNTER29H = 0xc9d, /**< 0xc9d - hpmcounter29h (r/w): Hardware performance monitor 29 counter high word */
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CSR_HPMCOUNTER30H = 0xc9e, /**< 0xc9e - hpmcounter30h (r/w): Hardware performance monitor 30 counter high word */
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CSR_HPMCOUNTER31H = 0xc9f, /**< 0xc9f - hpmcounter31h (r/w): Hardware performance monitor 31 counter high word */
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CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
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CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
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CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
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CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
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CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
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CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
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CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
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CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
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* CPU <b>mcounteren</b> CSR (r/w): Machine counter enable (RISC-V spec.)
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* CPU <b>mcounteren</b> CSR (r/w): Machine counter enable (RISC-V spec.)
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**************************************************************************/
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**************************************************************************/
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enum NEORV32_CSR_MCOUNTEREN_enum {
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enum NEORV32_CSR_MCOUNTEREN_enum {
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CSR_MCOUNTEREN_CY = 0, /**< CPU mcounteren CSR (0): CY - Allow access to cycle[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_CY = 0, /**< CPU mcounteren CSR (0): CY - Allow access to cycle[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_TM = 1, /**< CPU mcounteren CSR (1): TM - Allow access to time[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_TM = 1, /**< CPU mcounteren CSR (1): TM - Allow access to time[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_IR = 2, /**< CPU mcounteren CSR (2): IR - Allow access to instret[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_IR = 2 /**< CPU mcounteren CSR (2): IR - Allow access to instret[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM3 = 3, /**< CPU mcounteren CSR (3): HPM3 - Allow access to hpmcnt3[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM4 = 4, /**< CPU mcounteren CSR (4): HPM4 - Allow access to hpmcnt4[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM5 = 5, /**< CPU mcounteren CSR (5): HPM5 - Allow access to hpmcnt5[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM6 = 6, /**< CPU mcounteren CSR (6): HPM6 - Allow access to hpmcnt6[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM7 = 7, /**< CPU mcounteren CSR (7): HPM7 - Allow access to hpmcnt7[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM8 = 8, /**< CPU mcounteren CSR (8): HPM8 - Allow access to hpmcnt8[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM9 = 9, /**< CPU mcounteren CSR (9): HPM9 - Allow access to hpmcnt9[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM10 = 10, /**< CPU mcounteren CSR (10): HPM10 - Allow access to hpmcnt10[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM11 = 11, /**< CPU mcounteren CSR (11): HPM11 - Allow access to hpmcnt11[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM12 = 12, /**< CPU mcounteren CSR (12): HPM12 - Allow access to hpmcnt12[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM13 = 13, /**< CPU mcounteren CSR (13): HPM13 - Allow access to hpmcnt13[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM14 = 14, /**< CPU mcounteren CSR (14): HPM14 - Allow access to hpmcnt14[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM15 = 15, /**< CPU mcounteren CSR (15): HPM15 - Allow access to hpmcnt15[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM16 = 16, /**< CPU mcounteren CSR (16): HPM16 - Allow access to hpmcnt16[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM17 = 17, /**< CPU mcounteren CSR (17): HPM17 - Allow access to hpmcnt17[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM18 = 18, /**< CPU mcounteren CSR (18): HPM18 - Allow access to hpmcnt18[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM19 = 19, /**< CPU mcounteren CSR (19): HPM19 - Allow access to hpmcnt19[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM20 = 20, /**< CPU mcounteren CSR (20): HPM20 - Allow access to hpmcnt20[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM21 = 21, /**< CPU mcounteren CSR (21): HPM21 - Allow access to hpmcnt21[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM22 = 22, /**< CPU mcounteren CSR (22): HPM22 - Allow access to hpmcnt22[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM23 = 23, /**< CPU mcounteren CSR (23): HPM23 - Allow access to hpmcnt23[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM24 = 24, /**< CPU mcounteren CSR (24): HPM24 - Allow access to hpmcnt24[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM25 = 25, /**< CPU mcounteren CSR (25): HPM25 - Allow access to hpmcnt25[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM26 = 26, /**< CPU mcounteren CSR (26): HPM26 - Allow access to hpmcnt26[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM27 = 27, /**< CPU mcounteren CSR (27): HPM27 - Allow access to hpmcnt27[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM28 = 28, /**< CPU mcounteren CSR (28): HPM28 - Allow access to hpmcnt28[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM29 = 29, /**< CPU mcounteren CSR (29): HPM29 - Allow access to hpmcnt29[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM30 = 30, /**< CPU mcounteren CSR (30): HPM30 - Allow access to hpmcnt30[h] CSRs from U-mode when set (r/w) */
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CSR_MCOUNTEREN_HPM31 = 31 /**< CPU mcounteren CSR (31): HPM31 - Allow access to hpmcnt31[h] CSRs from U-mode when set (r/w) */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* CPU <b>mcountinhibit</b> CSR (r/w): Machine counter-inhibit (RISC-V spec.)
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* CPU <b>mcountinhibit</b> CSR (r/w): Machine counter-inhibit (RISC-V spec.)
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Line 372... |
CSR_MIP_FIRQ3P = 19, /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/-) */
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CSR_MIP_FIRQ3P = 19, /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/-) */
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CSR_MIP_FIRQ4P = 20, /**< CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/-) */
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CSR_MIP_FIRQ4P = 20, /**< CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/-) */
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CSR_MIP_FIRQ5P = 21, /**< CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/-) */
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CSR_MIP_FIRQ5P = 21, /**< CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/-) */
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CSR_MIP_FIRQ6P = 22, /**< CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/-) */
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CSR_MIP_FIRQ6P = 22, /**< CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/-) */
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CSR_MIP_FIRQ7P = 23, /**< CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/-) */
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CSR_MIP_FIRQ7P = 23, /**< CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/-) */
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CSR_MIP_FIRQ8P = 24, /**< CPU mip CSR (24): FIRQ8P - Fast interrupt channel 8 pending (r/-) */
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CSR_MIP_FIRQ8P = 24, /**< CPU mip CSR (24): FIRQ8P - Fast interrupt channel 8 pending (r/-) */
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CSR_MIP_FIRQ9P = 25, /**< CPU mip CSR (25): FIRQ9P - Fast interrupt channel 9 pending (r/-) */
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CSR_MIP_FIRQ9P = 25, /**< CPU mip CSR (25): FIRQ9P - Fast interrupt channel 9 pending (r/-) */
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CSR_MIP_FIRQ10P = 26, /**< CPU mip CSR (26): FIRQ10P - Fast interrupt channel 10 pending (r/-) */
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CSR_MIP_FIRQ10P = 26, /**< CPU mip CSR (26): FIRQ10P - Fast interrupt channel 10 pending (r/-) */
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CSR_MIP_FIRQ11P = 27, /**< CPU mip CSR (27): FIRQ11P - Fast interrupt channel 11 pending (r/-) */
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CSR_MIP_FIRQ11P = 27, /**< CPU mip CSR (27): FIRQ11P - Fast interrupt channel 11 pending (r/-) */
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CSR_MIP_FIRQ12P = 28, /**< CPU mip CSR (28): FIRQ12P - Fast interrupt channel 12 pending (r/-) */
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CSR_MIP_FIRQ12P = 28, /**< CPU mip CSR (28): FIRQ12P - Fast interrupt channel 12 pending (r/-) */
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Line 387... |
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/**********************************************************************//**
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/**********************************************************************//**
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* CPU <b>misa</b> CSR (r/-): Machine instruction set extensions (RISC-V spec.)
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* CPU <b>misa</b> CSR (r/-): Machine instruction set extensions (RISC-V spec.)
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**************************************************************************/
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**************************************************************************/
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enum NEORV32_CSR_MISA_enum {
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enum NEORV32_CSR_MISA_enum {
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CSR_MISA_A_EXT = 0, /**< CPU misa CSR (0): A: Atomic instructions CPU extension available (r/-)*/
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CSR_MISA_A = 0, /**< CPU misa CSR (0): A: Atomic instructions CPU extension available (r/-)*/
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CSR_MISA_B_EXT = 1, /**< CPU misa CSR (1): B: Bit manipulation CPU extension available (r/-)*/
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CSR_MISA_B = 1, /**< CPU misa CSR (1): B: Bit manipulation CPU extension available (r/-)*/
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CSR_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-)*/
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CSR_MISA_C = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-)*/
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CSR_MISA_D_EXT = 3, /**< CPU misa CSR (3): D: Double-precision floating-point extension available (r/-)*/
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CSR_MISA_D = 3, /**< CPU misa CSR (3): D: Double-precision floating-point extension available (r/-)*/
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CSR_MISA_E_EXT = 4, /**< CPU misa CSR (4): E: Embedded CPU extension available (r/-) */
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CSR_MISA_E = 4, /**< CPU misa CSR (4): E: Embedded CPU extension available (r/-) */
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CSR_MISA_F_EXT = 5, /**< CPU misa CSR (5): F: Single-precision floating-point extension available (r/-)*/
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CSR_MISA_F = 5, /**< CPU misa CSR (5): F: Single-precision floating-point extension available (r/-)*/
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CSR_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
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CSR_MISA_I = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
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CSR_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
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CSR_MISA_M = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
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CSR_MISA_U_EXT = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
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CSR_MISA_U = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
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CSR_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
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CSR_MISA_X = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
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CSR_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
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CSR_MISA_MXL_LO = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
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CSR_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
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CSR_MISA_MXL_HI = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* CPU <b>mzext</b> custom CSR (r/-): Implemented Z* CPU extensions
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* CPU <b>mzext</b> custom CSR (r/-): Implemented Z* CPU extensions
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**************************************************************************/
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**************************************************************************/
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enum NEORV32_CSR_MZEXT_enum {
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enum NEORV32_CSR_MZEXT_enum {
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CSR_MZEXT_ZICSR = 0, /**< CPU mzext CSR (0): Zicsr extension (I sub-extension) available when set (r/-) */
|
CSR_MZEXT_ZICSR = 0, /**< CPU mzext CSR (0): Zicsr extension (I sub-extension) available when set (r/-) */
|
CSR_MZEXT_ZIFENCEI = 1, /**< CPU mzext CSR (1): Zifencei extension (I sub-extension) available when set (r/-) */
|
CSR_MZEXT_ZIFENCEI = 1, /**< CPU mzext CSR (1): Zifencei extension (I sub-extension) available when set (r/-) */
|
//CSR_MZEXT_ZBB = 2, /**< CPU mzext CSR (2): Zbb extension (B sub-extension) available when set (r/-) */
|
CSR_MZEXT_ZMMUL = 2, /**< CPU mzext CSR (2): Zmmul extension (M sub-extension) available when set (r/-) */
|
//CSR_MZEXT_ZBS = 3, /**< CPU mzext CSR (3): Zbs extension (B sub-extension) available when set (r/-) */
|
|
//CSR_MZEXT_ZBA = 4, /**< CPU mzext CSR (4): Zba extension (B sub-extension) available when set (r/-) */
|
|
CSR_MZEXT_ZFINX = 5, /**< CPU mzext CSR (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
|
CSR_MZEXT_ZFINX = 5, /**< CPU mzext CSR (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
|
CSR_MZEXT_ZXSCNT = 6, /**< CPU mzext CSR (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
|
CSR_MZEXT_ZXSCNT = 6, /**< CPU mzext CSR (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
|
CSR_MZEXT_ZXNOCNT = 7, /**< CPU mzext CSR (7): Custom extension - NO CPU counters: "cycle" & "instret" CSRs are NOT available at all when set (r/-) */
|
CSR_MZEXT_ZXNOCNT = 7, /**< CPU mzext CSR (7): Custom extension - NO CPU counters: "cycle" & "instret" CSRs are NOT available at all when set (r/-) */
|
CSR_MZEXT_PMP = 8, /**< CPU mzext CSR (8): PMP (physical memory protection) extension available when set (r/-) */
|
CSR_MZEXT_PMP = 8, /**< CPU mzext CSR (8): PMP (physical memory protection) extension available when set (r/-) */
|
CSR_MZEXT_HPM = 9, /**< CPU mzext CSR (9): HPM (hardware performance monitors) extension available when set (r/-) */
|
CSR_MZEXT_HPM = 9, /**< CPU mzext CSR (9): HPM (hardware performance monitors) extension available when set (r/-) */
|
| Line 713... |
Line 626... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Pulse Width Modulation Controller (PWM)
|
* @name IO Device: Pulse Width Modulation Controller (PWM)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** PWM base address */
|
/** PWM base address */
|
#define PWM_BASE (0XFFFFFF80UL) // /**< PWM base address */
|
#define PWM_BASE (0xFFFFFE80UL) // /**< PWM base address */
|
/** PWM address space size in bytes */
|
/** PWM address space size in bytes */
|
#define PWM_SIZE (16*4) // /**< PWM address space size in bytes */
|
#define PWM_SIZE (16*4) // /**< PWM address space size in bytes */
|
|
|
/** PWM control register (r/w) */
|
/** PWM control register (r/w) */
|
#define PWM_CT (*(IO_REG32 (PWM_BASE + 0))) // r/w: control register
|
#define PWM_CT (*(IO_REG32 (PWM_BASE + 0))) // r/w: control register
|
| Line 761... |
Line 674... |
};
|
};
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: General Purpose Input/Output Port Unit (GPIO)
|
* @name IO Device: Stream link interface (SLINK)
|
**************************************************************************/
|
|
/**@{*/
|
|
/** GPIO base address */
|
|
#define GPIO_BASE (0xFFFFFF80UL) // /**< GPIO base address */
|
|
/** GPIO address space size in bytes */
|
|
#define GPIO_SIZE (2*4) // /**< GPIO address space size in bytes */
|
|
|
|
/** read access: GPIO parallel input port 32-bit (r/-), write_access: pin-change IRQ for each input pin (-/w) */
|
|
#define GPIO_INPUT (*(IO_REG32 (GPIO_BASE + 0)))
|
|
/** GPIO parallel output port 32-bit (r/w) */
|
|
#define GPIO_OUTPUT (*(IO_REG32 (GPIO_BASE + 4)))
|
|
/**@}*/
|
|
|
|
|
|
/**********************************************************************//**
|
|
* @name IO Device: True Random Number Generator (TRNG)
|
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** TRNG base address */
|
/** SLINK base address */
|
#define TRNG_BASE (0xFFFFFF88UL) // /**< TRNG base address */
|
#define SLINK_BASE (0xFFFFFEC0UL) // /**< SLINK base address */
|
/** TRNG address space size in bytes */
|
/** SLINK address space size in bytes */
|
#define TRNG_SIZE (1*4) // /**< TRNG address space size in bytes */
|
#define SLINK_SIZE (16*4) // /**< SLINK address space size in bytes */
|
|
|
/** TRNG control/data register (r/w) */
|
/** SLINK control register (r/w) */
|
#define TRNG_CT (*(IO_REG32 (TRNG_BASE + 0)))
|
#define SLINK_CT (*(IO_REG32 (SLINK_BASE + 0))) // r/w: control register
|
|
/** stream link 0 (r/w) */
|
/** TRNG control/data register bits */
|
#define SLINK_CH0 (*(IO_REG32 (SLINK_BASE + 32 + 0))) // r/w: link 0
|
enum NEORV32_TRNG_CT_enum {
|
/** stream link 1 (r/w) */
|
TRNG_CT_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data byte LSB */
|
#define SLINK_CH1 (*(IO_REG32 (SLINK_BASE + 32 + 4))) // r/w: link 1
|
TRNG_CT_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data byte MSB */
|
/** stream link 2 (r/w) */
|
|
#define SLINK_CH2 (*(IO_REG32 (SLINK_BASE + 32 + 8))) // r/w: link 2
|
|
/** stream link 3 (r/w) */
|
|
#define SLINK_CH3 (*(IO_REG32 (SLINK_BASE + 32 + 12))) // r/w: link 3
|
|
/** stream link 4 (r/w) */
|
|
#define SLINK_CH4 (*(IO_REG32 (SLINK_BASE + 32 + 16))) // r/w: link 4
|
|
/** stream link 5 (r/w) */
|
|
#define SLINK_CH5 (*(IO_REG32 (SLINK_BASE + 32 + 20))) // r/w: link 5
|
|
/** stream link 6 (r/w) */
|
|
#define SLINK_CH6 (*(IO_REG32 (SLINK_BASE + 32 + 24))) // r/w: link 6
|
|
/** stream link 7 (r/w) */
|
|
#define SLINK_CH7 (*(IO_REG32 (SLINK_BASE + 32 + 28))) // r/w: link 7
|
|
|
|
/** SLINK control register bits */
|
|
enum NEORV32_SLINK_CT_enum {
|
|
SLINK_CT_RX0_AVAIL = 0, /**< SLINK control register(0) (r/-): RX link 0 data available */
|
|
SLINK_CT_RX1_AVAIL = 1, /**< SLINK control register(1) (r/-): RX link 1 data available */
|
|
SLINK_CT_RX2_AVAIL = 2, /**< SLINK control register(2) (r/-): RX link 2 data available */
|
|
SLINK_CT_RX3_AVAIL = 3, /**< SLINK control register(3) (r/-): RX link 3 data available */
|
|
SLINK_CT_RX4_AVAIL = 4, /**< SLINK control register(4) (r/-): RX link 4 data available */
|
|
SLINK_CT_RX5_AVAIL = 5, /**< SLINK control register(5) (r/-): RX link 5 data available */
|
|
SLINK_CT_RX6_AVAIL = 6, /**< SLINK control register(6) (r/-): RX link 6 data available */
|
|
SLINK_CT_RX7_AVAIL = 7, /**< SLINK control register(7) (r/-): RX link 7 data available */
|
|
|
|
SLINK_CT_TX0_FREE = 8, /**< SLINK control register(8) (r/-): RT link 0 ready to send */
|
|
SLINK_CT_TX1_FREE = 9, /**< SLINK control register(9) (r/-): RT link 1 ready to send */
|
|
SLINK_CT_TX2_FREE = 10, /**< SLINK control register(10) (r/-): RT link 2 ready to send */
|
|
SLINK_CT_TX3_FREE = 11, /**< SLINK control register(11) (r/-): RT link 3 ready to send */
|
|
SLINK_CT_TX4_FREE = 12, /**< SLINK control register(12) (r/-): RT link 4 ready to send */
|
|
SLINK_CT_TX5_FREE = 13, /**< SLINK control register(13) (r/-): RT link 5 ready to send */
|
|
SLINK_CT_TX6_FREE = 14, /**< SLINK control register(14) (r/-): RT link 6 ready to send */
|
|
SLINK_CT_TX7_FREE = 15, /**< SLINK control register(15) (r/-): RT link 7 ready to send */
|
|
|
|
SLINK_CT_RX_NUM0 = 16, /**< SLINK control register(16) (r/-): number of implemented RX links -1 bit 0 */
|
|
SLINK_CT_RX_NUM1 = 17, /**< SLINK control register(17) (r/-): number of implemented RX links -1 bit 1 */
|
|
SLINK_CT_RX_NUM2 = 18, /**< SLINK control register(18) (r/-): number of implemented RX links -1 bit 2 */
|
|
|
|
SLINK_CT_TX_NUM0 = 19, /**< SLINK control register(19) (r/-): number of implemented TX links -1bit 0 */
|
|
SLINK_CT_TX_NUM1 = 20, /**< SLINK control register(20) (r/-): number of implemented TX links -1bit 1 */
|
|
SLINK_CT_TX_NUM2 = 21, /**< SLINK control register(21) (r/-): number of implemented TX links -1bit 2 */
|
|
|
|
SLINK_CT_RX_FIFO_S0 = 22, /**< SLINK control register(22) (r/-): log2(RX FIFO size) bit 0 */
|
|
SLINK_CT_RX_FIFO_S1 = 23, /**< SLINK control register(23) (r/-): log2(RX FIFO size) bit 1 */
|
|
SLINK_CT_RX_FIFO_S2 = 24, /**< SLINK control register(24) (r/-): log2(RX FIFO size) bit 2 */
|
|
SLINK_CT_RX_FIFO_S3 = 25, /**< SLINK control register(25) (r/-): log2(RX FIFO size) bit 3 */
|
|
|
|
SLINK_CT_TX_FIFO_S0 = 26, /**< SLINK control register(26) (r/-): log2(TX FIFO size) bit 0 */
|
|
SLINK_CT_TX_FIFO_S1 = 27, /**< SLINK control register(27) (r/-): log2(TX FIFO size) bit 1 */
|
|
SLINK_CT_TX_FIFO_S2 = 28, /**< SLINK control register(28) (r/-): log2(TX FIFO size) bit 2 */
|
|
SLINK_CT_TX_FIFO_S3 = 29, /**< SLINK control register(29) (r/-): log2(TX FIFO size) bit 3 */
|
|
|
TRNG_CT_EN = 30, /**< TRNG data/control register(30) (r/w): TRNG enable */
|
SLINK_CT_EN = 31 /**< SLINK control register(31) (r/w): SLINK controller enable */
|
TRNG_CT_VALID = 31 /**< TRNG data/control register(31) (r/-): Random data output valid */
|
|
};
|
};
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Watchdog Timer (WDT)
|
* @name IO Device: External Interrupt Controller (XIRQ)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** WDT base address */
|
/** XIRQ base address */
|
#define WDT_BASE (0xFFFFFF8CUL) // /**< WDT base address */
|
#define XIRQ_BASE (0xFFFFFF80UL) // /**< XIRQ base address */
|
/** WDT address space size in bytes */
|
/** XIRQ address space size in bytes */
|
#define WDT_SIZE (1*4) // /**< WDT address space size in bytes */
|
#define XIRQ_SIZE (4*4) // /**< XIRQ address space size in bytes */
|
|
|
/** Watchdog control register (r/w) */
|
/** XIRQ IRQ input enable register (r/w) */
|
#define WDT_CT (*(IO_REG32 (WDT_BASE + 0)))
|
#define XIRQ_IER (*(IO_REG32 (XIRQ_BASE + 0)))
|
|
/** XIRQ pending IRQ register /ack/clear (r/w) */
|
/** WTD control register bits */
|
#define XIRQ_IPR (*(IO_REG32 (XIRQ_BASE + 4)))
|
enum NEORV32_WDT_CT_enum {
|
/** EXTIRW (time compare register) low word (r/w) */
|
WDT_CT_EN = 0, /**< WDT control register(0) (r/w): Watchdog enable */
|
#define XIRQ_SCR (*(IO_REG32 (XIRQ_BASE + 8)))
|
WDT_CT_CLK_SEL0 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 0 */
|
// reserved
|
WDT_CT_CLK_SEL1 = 2, /**< WDT control register(2) (r/w): Clock prescaler select bit 1 */
|
//#define XIRQ_reserved (*(IO_REG32 (XIRQ_BASE + 12)))
|
WDT_CT_CLK_SEL2 = 3, /**< WDT control register(3) (r/w): Clock prescaler select bit 2 */
|
|
WDT_CT_MODE = 4, /**< WDT control register(4) (r/w): Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset */
|
|
WDT_CT_RCAUSE = 5, /**< WDT control register(5) (r/-): Cause of last system reset: 0=external reset, 1=watchdog */
|
|
WDT_CT_RESET = 6, /**< WDT control register(6) (-/w): Reset WDT counter when set, auto-clears */
|
|
WDT_CT_FORCE = 7, /**< WDT control register(7) (-/w): Force WDT action, auto-clears */
|
|
WDT_CT_LOCK = 8 /**< WDT control register(8) (r/w): Lock write access to control register, clears on reset (HW or WDT) only */
|
|
};
|
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Machine System Timer (MTIME)
|
* @name IO Device: Machine System Timer (MTIME)
|
| Line 1008... |
Line 946... |
};
|
};
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Numerically-Controlled Oscillator (NCO)
|
* @name IO Device: True Random Number Generator (TRNG)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** NCO base address */
|
/** TRNG base address */
|
#define NCO_BASE (0xFFFFFFC0UL) // /**< NCO base address */
|
#define TRNG_BASE (0xFFFFFFB8UL) // /**< TRNG base address */
|
/** NCO address space size in bytes */
|
/** TRNG address space size in bytes */
|
#define NCO_SIZE (4*4) // /**< NCO address space size in bytes */
|
#define TRNG_SIZE (1*4) // /**< TRNG address space size in bytes */
|
|
|
/** NCO control register (r/w) */
|
/** TRNG control/data register (r/w) */
|
#define NCO_CT (*(IO_REG32 (NCO_BASE + 0))) // r/w: control register
|
#define TRNG_CT (*(IO_REG32 (TRNG_BASE + 0)))
|
/** NCO channel 0 tuning word (r/w) */
|
|
#define NCO_TUNE_CH0 (*(IO_REG32 (NCO_BASE + 4))) // r/w: tuning word channel 0
|
/** TRNG control/data register bits */
|
/** NCO channel 1 tuning word (r/w) */
|
enum NEORV32_TRNG_CT_enum {
|
#define NCO_TUNE_CH1 (*(IO_REG32 (NCO_BASE + 8))) // r/w: tuning word channel 1
|
TRNG_CT_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data byte LSB */
|
/** NCO channel 2 tuning word (r/w) */
|
TRNG_CT_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data byte MSB */
|
#define NCO_TUNE_CH2 (*(IO_REG32 (NCO_BASE + 12))) // r/w: tuning word channel 2
|
|
|
TRNG_CT_EN = 30, /**< TRNG data/control register(30) (r/w): TRNG enable */
|
/** NCO control register bits */
|
TRNG_CT_VALID = 31 /**< TRNG data/control register(31) (r/-): Random data output valid */
|
enum NEORV32_NCO_CT_enum {
|
|
NCO_CT_EN = 0, /**< NCO control register(0) (r/w): NCO global enable */
|
|
// channel 0
|
|
NCO_CT_CH0_MODE = 1, /**< NCO control register(1) - channel 0 (r/w): Output mode (0=fixed 50% duty cycle; 1=pulse mode) */
|
|
NCO_CT_CH0_IDLE_POL = 2, /**< NCO control register(2) - channel 0 (r/w): Output idle polarity (0=low, 1=high) */
|
|
NCO_CT_CH0_OE = 3, /**< NCO control register(3) - channel 0 (r/w): Enable processor output pin */
|
|
NCO_CT_CH0_OUTPUT = 4, /**< NCO control register(4) - channel 0 (r/-): Current channel output state */
|
|
NCO_CT_CH0_PRSC0 = 5, /**< NCO control register(5) - channel 0 (r/w): Clock prescaler select bit 0 */
|
|
NCO_CT_CH0_PRSC1 = 6, /**< NCO control register(6) - channel 0 (r/w): Clock prescaler select bit 1 */
|
|
NCO_CT_CH0_PRSC2 = 7, /**< NCO control register(7) - channel 0 (r/w): Clock prescaler select bit 2 */
|
|
NCO_CT_CH0_PULSE0 = 8, /**< NCO control register(8) - channel 0 (r/w): Pulse-mode: Pulse length select bit 0 */
|
|
NCO_CT_CH0_PULSE1 = 9, /**< NCO control register(9) - channel 0 (r/w): Pulse-mode: Pulse length select bit 1 */
|
|
NCO_CT_CH0_PULSE2 = 10, /**< NCO control register(10) - channel 0 (r/w): Pulse-mode: Pulse length select bit 2 */
|
|
// channel 1
|
|
NCO_CT_CH1_MODE = 11, /**< NCO control register(11) - channel 1 (r/w): Output mode (0=fixed 50% duty cycle; 1=pulse mode) */
|
|
NCO_CT_CH1_IDLE_POL = 12, /**< NCO control register(12) - channel 1 (r/w): Output idle polarity (0=low, 1=high) */
|
|
NCO_CT_CH1_OE = 13, /**< NCO control register(13) - channel 1 (r/w): Enable processor output pin */
|
|
NCO_CT_CH1_OUTPUT = 14, /**< NCO control register(14) - channel 1 (r/-): Current channel output state */
|
|
NCO_CT_CH1_PRSC0 = 15, /**< NCO control register(15) - channel 1 (r/w): Clock prescaler select bit 0 */
|
|
NCO_CT_CH1_PRSC1 = 16, /**< NCO control register(16) - channel 1 (r/w): Clock prescaler select bit 1 */
|
|
NCO_CT_CH1_PRSC2 = 17, /**< NCO control register(17) - channel 1 (r/w): Clock prescaler select bit 2 */
|
|
NCO_CT_CH1_PULSE0 = 18, /**< NCO control register(18) - channel 1 (r/w): Pulse-mode: Pulse length select bit 0 */
|
|
NCO_CT_CH1_PULSE1 = 19, /**< NCO control register(19) - channel 1 (r/w): Pulse-mode: Pulse length select bit 1 */
|
|
NCO_CT_CH1_PULSE2 = 20, /**< NCO control register(20) - channel 1 (r/w): Pulse-mode: Pulse length select bit 2 */
|
|
// channel 2
|
|
NCO_CT_CH2_MODE = 21, /**< NCO control register(21) - channel 2 (r/w): Output mode (0=fixed 50% duty cycle; 1=pulse mode) */
|
|
NCO_CT_CH2_IDLE_POL = 22, /**< NCO control register(22) - channel 2 (r/w): Output idle polarity (0=low, 1=high) */
|
|
NCO_CT_CH2_OE = 23, /**< NCO control register(23) - channel 2 (r/w): Enable processor output pin */
|
|
NCO_CT_CH2_OUTPUT = 24, /**< NCO control register(24) - channel 2 (r/-): Current channel output state */
|
|
NCO_CT_CH2_PRSC0 = 25, /**< NCO control register(25) - channel 2 (r/w): Clock prescaler select bit 0 */
|
|
NCO_CT_CH2_PRSC1 = 26, /**< NCO control register(26) - channel 2 (r/w): Clock prescaler select bit 1 */
|
|
NCO_CT_CH2_PRSC2 = 27, /**< NCO control register(27) - channel 2 (r/w): Clock prescaler select bit 2 */
|
|
NCO_CT_CH2_PULSE0 = 28, /**< NCO control register(28) - channel 2 (r/w): Pulse-mode: Pulse length select bit 0 */
|
|
NCO_CT_CH2_PULSE1 = 29, /**< NCO control register(29) - channel 2 (r/w): Pulse-mode: Pulse length select bit 1 */
|
|
NCO_CT_CH2_PULSE2 = 20 /**< NCO control register(30) - channel 2 (r/w): Pulse-mode: Pulse length select bit 2 */
|
|
};
|
};
|
|
/**@}*/
|
|
|
/** Size of one "channel entry" in control register in bits */
|
|
#define NCO_CHX_WIDTH 10 // Size of one "channel entry" in control register in bits
|
/**********************************************************************//**
|
|
* @name IO Device: Watchdog Timer (WDT)
|
|
**************************************************************************/
|
|
/**@{*/
|
|
/** WDT base address */
|
|
#define WDT_BASE (0xFFFFFFBCUL) // /**< WDT base address */
|
|
/** WDT address space size in bytes */
|
|
#define WDT_SIZE (1*4) // /**< WDT address space size in bytes */
|
|
|
|
/** Watchdog control register (r/w) */
|
|
#define WDT_CT (*(IO_REG32 (WDT_BASE + 0)))
|
|
|
|
/** WTD control register bits */
|
|
enum NEORV32_WDT_CT_enum {
|
|
WDT_CT_EN = 0, /**< WDT control register(0) (r/w): Watchdog enable */
|
|
WDT_CT_CLK_SEL0 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 0 */
|
|
WDT_CT_CLK_SEL1 = 2, /**< WDT control register(2) (r/w): Clock prescaler select bit 1 */
|
|
WDT_CT_CLK_SEL2 = 3, /**< WDT control register(3) (r/w): Clock prescaler select bit 2 */
|
|
WDT_CT_MODE = 4, /**< WDT control register(4) (r/w): Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset */
|
|
WDT_CT_RCAUSE = 5, /**< WDT control register(5) (r/-): Cause of last system reset: 0=external reset, 1=watchdog */
|
|
WDT_CT_RESET = 6, /**< WDT control register(6) (-/w): Reset WDT counter when set, auto-clears */
|
|
WDT_CT_FORCE = 7, /**< WDT control register(7) (-/w): Force WDT action, auto-clears */
|
|
WDT_CT_LOCK = 8 /**< WDT control register(8) (r/w): Lock write access to control register, clears on reset (HW or WDT) only */
|
|
};
|
|
/**@}*/
|
|
|
|
|
|
/**********************************************************************//**
|
|
* @name IO Device: General Purpose Input/Output Port Unit (GPIO)
|
|
**************************************************************************/
|
|
/**@{*/
|
|
/** GPIO base address */
|
|
#define GPIO_BASE (0xFFFFFFC0UL) // /**< GPIO base address */
|
|
/** GPIO address space size in bytes */
|
|
#define GPIO_SIZE (4*4) // /**< GPIO address space size in bytes */
|
|
|
|
/** GPIO parallel input port lower 32-bit (r/-) */
|
|
#define GPIO_INPUT_LO (*(IO_REG32 (GPIO_BASE + 0)))
|
|
/** GPIO parallel input port upper 32-bit (r/-) */
|
|
#define GPIO_INPUT_HI (*(IO_REG32 (GPIO_BASE + 4)))
|
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/** GPIO parallel output port lower 32-bit (r/w) */
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#define GPIO_OUTPUT_LO (*(IO_REG32 (GPIO_BASE + 8)))
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/** GPIO parallel output port upper 32-bit (r/w) */
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#define GPIO_OUTPUT_HI (*(IO_REG32 (GPIO_BASE + 12)))
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/** GPIO parallel input 64-bit access (r/-) */
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#define GPIO_INPUT (*(IO_REG64 (&GPIO_INPUT_LO)))
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/** GPIO parallel output 64-bit access (r/w) */
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#define GPIO_OUTPUT (*(IO_REG64 (&GPIO_OUTPUT_LO)))
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/**@}*/
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/**@}*/
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/**********************************************************************//**
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/**********************************************************************//**
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* @name IO Device: Smart LED Hardware Interface (NEOLED)
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* @name IO Device: Smart LED Hardware Interface (NEOLED)
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| Line 1151... |
Line 1103... |
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/**********************************************************************//**
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/**********************************************************************//**
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* SYSINFO_FEATURES (r/-): Implemented processor devices/features
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* SYSINFO_FEATURES (r/-): Implemented processor devices/features
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**************************************************************************/
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**************************************************************************/
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enum NEORV32_SYSINFO_FEATURES_enum {
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enum NEORV32_SYSINFO_FEATURES_enum {
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SYSINFO_FEATURES_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_EN generic) */
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SYSINFO_FEATURES_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
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SYSINFO_FEATURES_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
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SYSINFO_FEATURES_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
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SYSINFO_FEATURES_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
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SYSINFO_FEATURES_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
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SYSINFO_FEATURES_MEM_INT_IMEM_ROM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
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SYSINFO_FEATURES_MEM_INT_DMEM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */
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SYSINFO_FEATURES_MEM_INT_DMEM = 4, /**< SYSINFO_FEATURES (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */
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SYSINFO_FEATURES_MEM_EXT_ENDIAN = 4, /**< SYSINFO_FEATURES (4) (r/-): External bus interface uses BIG-endian byte-order when 1 (via package.xbus_big_endian_c constant) */
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SYSINFO_FEATURES_MEM_EXT_ENDIAN = 5, /**< SYSINFO_FEATURES (5) (r/-): External bus interface uses BIG-endian byte-order when 1 (via package.xbus_big_endian_c constant) */
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SYSINFO_FEATURES_ICACHE = 5, /**< SYSINFO_FEATURES (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */
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SYSINFO_FEATURES_ICACHE = 6, /**< SYSINFO_FEATURES (6) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */
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SYSINFO_FEATURES_OCD = 14, /**< SYSINFO_FEATURES (14) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */
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SYSINFO_FEATURES_OCD = 14, /**< SYSINFO_FEATURES (14) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */
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SYSINFO_FEATURES_HW_RESET = 15, /**< SYSINFO_FEATURES (15) (r/-): Dedicated hardware reset of core registers implemented when 1 (via package's dedicated_reset_c constant) */
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SYSINFO_FEATURES_HW_RESET = 15, /**< SYSINFO_FEATURES (15) (r/-): Dedicated hardware reset of core registers implemented when 1 (via package's dedicated_reset_c constant) */
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SYSINFO_FEATURES_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */
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SYSINFO_FEATURES_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */
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| Line 1171... |
Line 1122... |
SYSINFO_FEATURES_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) */
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SYSINFO_FEATURES_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) */
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SYSINFO_FEATURES_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */
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SYSINFO_FEATURES_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */
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SYSINFO_FEATURES_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */
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SYSINFO_FEATURES_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */
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SYSINFO_FEATURES_IO_CFS = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */
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SYSINFO_FEATURES_IO_CFS = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */
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SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */
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SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */
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SYSINFO_FEATURES_IO_NCO = 25, /**< SYSINFO_FEATURES (25) (r/-): Numerically-controlled oscillator implemented when 1 (via IO_NCO_EN generic) */
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SYSINFO_FEATURES_IO_SLINK = 25, /**< SYSINFO_FEATURES (25) (r/-): Stream link interface implemented when 1 (via SLINK_NUM_RX & SLINK_NUM_TX generics) */
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SYSINFO_FEATURES_IO_UART1 = 26, /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
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SYSINFO_FEATURES_IO_UART1 = 26, /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
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SYSINFO_FEATURES_IO_NEOLED = 27 /**< SYSINFO_FEATURES (27) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */
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SYSINFO_FEATURES_IO_NEOLED = 27, /**< SYSINFO_FEATURES (27) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */
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SYSINFO_FEATURES_IO_XIRQ = 28 /**< SYSINFO_FEATURES (28) (r/-): External interrupt controller implemented when 1 (via XIRQ_NUM_IO generic) */
|
};
|
};
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* SYSINFO_CACHE (r/-): Cache configuration
|
* SYSINFO_CACHE (r/-): Cache configuration
|
**************************************************************************/
|
**************************************************************************/
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| Line 1218... |
Line 1170... |
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// io/peripheral devices
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// io/peripheral devices
|
#include "neorv32_cfs.h"
|
#include "neorv32_cfs.h"
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#include "neorv32_gpio.h"
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#include "neorv32_gpio.h"
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#include "neorv32_mtime.h"
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#include "neorv32_mtime.h"
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#include "neorv32_nco.h"
|
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#include "neorv32_neoled.h"
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#include "neorv32_neoled.h"
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#include "neorv32_pwm.h"
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#include "neorv32_pwm.h"
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#include "neorv32_slink.h"
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#include "neorv32_spi.h"
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#include "neorv32_spi.h"
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#include "neorv32_trng.h"
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#include "neorv32_trng.h"
|
#include "neorv32_twi.h"
|
#include "neorv32_twi.h"
|
#include "neorv32_uart.h"
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#include "neorv32_uart.h"
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#include "neorv32_wdt.h"
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#include "neorv32_wdt.h"
|
|
#include "neorv32_xirq.h"
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|
|
|
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|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
#endif // neorv32_h
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#endif // neorv32_h
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No newline at end of file
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