| Line 66... |
Line 66... |
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */
|
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */
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CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */
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CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */
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CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */
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CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */
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CSR_MCOUNTEREN = 0x306, /**< 0x305 - mcounteren (r/w): Machine counter enable register (controls access rights from U-mode) */
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CSR_MCOUNTEREN = 0x306, /**< 0x305 - mcounteren (r/w): Machine counter enable register (controls access rights from U-mode) */
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|
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CSR_MSTATUSH = 0x310, /**< 0x310 - mstatush (r/h): Machine status register - high word */
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|
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CSR_MCOUNTINHIBIT = 0x320, /**< 0x320 - mcountinhibit (r/w): Machine counter-inhibit register */
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CSR_MCOUNTINHIBIT = 0x320, /**< 0x320 - mcountinhibit (r/w): Machine counter-inhibit register */
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CSR_MHPMEVENT3 = 0x323, /**< 0x323 - mhpmevent3 (r/w): Machine hardware performance monitor event selector 3 */
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CSR_MHPMEVENT3 = 0x323, /**< 0x323 - mhpmevent3 (r/w): Machine hardware performance monitor event selector 3 */
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CSR_MHPMEVENT4 = 0x324, /**< 0x324 - mhpmevent4 (r/w): Machine hardware performance monitor event selector 4 */
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CSR_MHPMEVENT4 = 0x324, /**< 0x324 - mhpmevent4 (r/w): Machine hardware performance monitor event selector 4 */
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CSR_MHPMEVENT5 = 0x325, /**< 0x325 - mhpmevent5 (r/w): Machine hardware performance monitor event selector 5 */
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CSR_MHPMEVENT5 = 0x325, /**< 0x325 - mhpmevent5 (r/w): Machine hardware performance monitor event selector 5 */
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| Line 264... |
Line 266... |
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CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
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CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
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CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
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CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
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CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
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CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
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CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
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CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
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CSR_MCONFIGPTR = 0xf15, /**< 0xf15 - mconfigptr (r/-): Machine configuration pointer register */
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|
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CSR_MZEXT = 0xfc0 /**< 0xfc0 - mzext (custom CSR) (r/-): Available Z* CPU extensions */
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CSR_MZEXT = 0xfc0 /**< 0xfc0 - mzext (custom CSR) (r/-): Available Z* CPU extensions */
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};
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};
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|
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| Line 276... |
Line 279... |
**************************************************************************/
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**************************************************************************/
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enum NEORV32_CSR_MSTATUS_enum {
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enum NEORV32_CSR_MSTATUS_enum {
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CSR_MSTATUS_MIE = 3, /**< CPU mstatus CSR (3): MIE - Machine interrupt enable bit (r/w) */
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CSR_MSTATUS_MIE = 3, /**< CPU mstatus CSR (3): MIE - Machine interrupt enable bit (r/w) */
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CSR_MSTATUS_MPIE = 7, /**< CPU mstatus CSR (7): MPIE - Machine previous interrupt enable bit (r/w) */
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CSR_MSTATUS_MPIE = 7, /**< CPU mstatus CSR (7): MPIE - Machine previous interrupt enable bit (r/w) */
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CSR_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) */
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CSR_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) */
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CSR_MSTATUS_MPP_H = 12 /**< CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) */
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CSR_MSTATUS_MPP_H = 12, /**< CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) */
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CSR_MSTATUS_FS_L = 13, /**< CPU mstatus CSR (13): FS_L - FPU state bit low (r/w) */
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CSR_MSTATUS_FS_H = 14, /**< CPU mstatus CSR (14): FS_H - FPU state bit high (r/w) */
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CSR_MSTATUS_TW = 21, /**< CPU mstatus CSR (21): TW - timeout wait (trigger illegal instruction exception if WFI is executed outside of m-mode when set) (r/w) */
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CSR_MSTATUS_SD = 31 /**< CPU mstatus CSR (31): SD - extension's state summary (set = non-clean) (r/-) */
|
};
|
};
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* CPU <b>mcounteren</b> CSR (r/w): Machine counter enable (RISC-V spec.)
|
* CPU <b>mcounteren</b> CSR (r/w): Machine counter enable (RISC-V spec.)
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| Line 684... |
Line 691... |
/** SLINK address space size in bytes */
|
/** SLINK address space size in bytes */
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#define SLINK_SIZE (16*4) // /**< SLINK address space size in bytes */
|
#define SLINK_SIZE (16*4) // /**< SLINK address space size in bytes */
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|
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/** SLINK control register (r/w) */
|
/** SLINK control register (r/w) */
|
#define SLINK_CT (*(IO_REG32 (SLINK_BASE + 0))) // r/w: control register
|
#define SLINK_CT (*(IO_REG32 (SLINK_BASE + 0))) // r/w: control register
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/** SLINK status register (r/-) */
|
|
#define SLINK_STATUS (*(IO_REG32 (SLINK_BASE + 16))) // r/-: status register
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/** stream link 0 (r/w) */
|
/** stream link 0 (r/w) */
|
#define SLINK_CH0 (*(IO_REG32 (SLINK_BASE + 32 + 0))) // r/w: link 0
|
#define SLINK_CH0 (*(IO_REG32 (SLINK_BASE + 32 + 0))) // r/w: link 0
|
/** stream link 1 (r/w) */
|
/** stream link 1 (r/w) */
|
#define SLINK_CH1 (*(IO_REG32 (SLINK_BASE + 32 + 4))) // r/w: link 1
|
#define SLINK_CH1 (*(IO_REG32 (SLINK_BASE + 32 + 4))) // r/w: link 1
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/** stream link 2 (r/w) */
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/** stream link 2 (r/w) */
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| Line 703... |
Line 712... |
/** stream link 7 (r/w) */
|
/** stream link 7 (r/w) */
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#define SLINK_CH7 (*(IO_REG32 (SLINK_BASE + 32 + 28))) // r/w: link 7
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#define SLINK_CH7 (*(IO_REG32 (SLINK_BASE + 32 + 28))) // r/w: link 7
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|
|
/** SLINK control register bits */
|
/** SLINK control register bits */
|
enum NEORV32_SLINK_CT_enum {
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enum NEORV32_SLINK_CT_enum {
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SLINK_CT_RX0_AVAIL = 0, /**< SLINK control register(0) (r/-): RX link 0 data available */
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SLINK_CT_RX_NUM0 = 0, /**< SLINK control register(0) (r/-): number of implemented RX links bit 0 */
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SLINK_CT_RX1_AVAIL = 1, /**< SLINK control register(1) (r/-): RX link 1 data available */
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SLINK_CT_RX_NUM1 = 1, /**< SLINK control register(1) (r/-): number of implemented RX links bit 1 */
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SLINK_CT_RX2_AVAIL = 2, /**< SLINK control register(2) (r/-): RX link 2 data available */
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SLINK_CT_RX_NUM2 = 2, /**< SLINK control register(2) (r/-): number of implemented RX links bit 2 */
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SLINK_CT_RX3_AVAIL = 3, /**< SLINK control register(3) (r/-): RX link 3 data available */
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SLINK_CT_RX_NUM3 = 3, /**< SLINK control register(3) (r/-): number of implemented RX links bit 3 */
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SLINK_CT_RX4_AVAIL = 4, /**< SLINK control register(4) (r/-): RX link 4 data available */
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SLINK_CT_RX5_AVAIL = 5, /**< SLINK control register(5) (r/-): RX link 5 data available */
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SLINK_CT_TX_NUM0 = 4, /**< SLINK control register(4) (r/-): number of implemented TX links bit 0 */
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SLINK_CT_RX6_AVAIL = 6, /**< SLINK control register(6) (r/-): RX link 6 data available */
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SLINK_CT_TX_NUM1 = 5, /**< SLINK control register(5) (r/-): number of implemented TX links bit 1 */
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SLINK_CT_RX7_AVAIL = 7, /**< SLINK control register(7) (r/-): RX link 7 data available */
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SLINK_CT_TX_NUM2 = 6, /**< SLINK control register(6) (r/-): number of implemented TX links bit 2 */
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SLINK_CT_TX_NUM3 = 7, /**< SLINK control register(7) (r/-): number of implemented TX links bit 3 */
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SLINK_CT_TX0_FREE = 8, /**< SLINK control register(8) (r/-): RT link 0 ready to send */
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SLINK_CT_TX1_FREE = 9, /**< SLINK control register(9) (r/-): RT link 1 ready to send */
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SLINK_CT_RX_FIFO_S0 = 8, /**< SLINK control register( 8) (r/-): log2(RX FIFO size) bit 0 */
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SLINK_CT_TX2_FREE = 10, /**< SLINK control register(10) (r/-): RT link 2 ready to send */
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SLINK_CT_RX_FIFO_S1 = 9, /**< SLINK control register( 9) (r/-): log2(RX FIFO size) bit 1 */
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SLINK_CT_TX3_FREE = 11, /**< SLINK control register(11) (r/-): RT link 3 ready to send */
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SLINK_CT_RX_FIFO_S2 = 10, /**< SLINK control register(10) (r/-): log2(RX FIFO size) bit 2 */
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SLINK_CT_TX4_FREE = 12, /**< SLINK control register(12) (r/-): RT link 4 ready to send */
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SLINK_CT_RX_FIFO_S3 = 11, /**< SLINK control register(11) (r/-): log2(RX FIFO size) bit 3 */
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SLINK_CT_TX5_FREE = 13, /**< SLINK control register(13) (r/-): RT link 5 ready to send */
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SLINK_CT_TX6_FREE = 14, /**< SLINK control register(14) (r/-): RT link 6 ready to send */
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SLINK_CT_TX_FIFO_S0 = 12, /**< SLINK control register(12) (r/-): log2(TX FIFO size) bit 0 */
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SLINK_CT_TX7_FREE = 15, /**< SLINK control register(15) (r/-): RT link 7 ready to send */
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SLINK_CT_TX_FIFO_S1 = 13, /**< SLINK control register(13) (r/-): log2(TX FIFO size) bit 1 */
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SLINK_CT_TX_FIFO_S2 = 14, /**< SLINK control register(14) (r/-): log2(TX FIFO size) bit 2 */
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SLINK_CT_RX_NUM0 = 16, /**< SLINK control register(16) (r/-): number of implemented RX links -1 bit 0 */
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SLINK_CT_TX_FIFO_S3 = 15, /**< SLINK control register(15) (r/-): log2(TX FIFO size) bit 3 */
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SLINK_CT_RX_NUM1 = 17, /**< SLINK control register(17) (r/-): number of implemented RX links -1 bit 1 */
|
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SLINK_CT_RX_NUM2 = 18, /**< SLINK control register(18) (r/-): number of implemented RX links -1 bit 2 */
|
SLINK_CT_EN = 31, /**< SLINK control register(0) (r/w): SLINK controller enable */
|
|
};
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SLINK_CT_TX_NUM0 = 19, /**< SLINK control register(19) (r/-): number of implemented TX links -1bit 0 */
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SLINK_CT_TX_NUM1 = 20, /**< SLINK control register(20) (r/-): number of implemented TX links -1bit 1 */
|
/** SLINK status register bits */
|
SLINK_CT_TX_NUM2 = 21, /**< SLINK control register(21) (r/-): number of implemented TX links -1bit 2 */
|
enum NEORV32_SLINK_STATUS_enum {
|
|
SLINK_STATUS_RX0_AVAIL = 0, /**< SLINK status register(0) (r/-): RX link 0 data available */
|
SLINK_CT_RX_FIFO_S0 = 22, /**< SLINK control register(22) (r/-): log2(RX FIFO size) bit 0 */
|
SLINK_STATUS_RX1_AVAIL = 1, /**< SLINK status register(1) (r/-): RX link 1 data available */
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SLINK_CT_RX_FIFO_S1 = 23, /**< SLINK control register(23) (r/-): log2(RX FIFO size) bit 1 */
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SLINK_STATUS_RX2_AVAIL = 2, /**< SLINK status register(2) (r/-): RX link 2 data available */
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SLINK_CT_RX_FIFO_S2 = 24, /**< SLINK control register(24) (r/-): log2(RX FIFO size) bit 2 */
|
SLINK_STATUS_RX3_AVAIL = 3, /**< SLINK status register(3) (r/-): RX link 3 data available */
|
SLINK_CT_RX_FIFO_S3 = 25, /**< SLINK control register(25) (r/-): log2(RX FIFO size) bit 3 */
|
SLINK_STATUS_RX4_AVAIL = 4, /**< SLINK status register(4) (r/-): RX link 4 data available */
|
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SLINK_STATUS_RX5_AVAIL = 5, /**< SLINK status register(5) (r/-): RX link 5 data available */
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SLINK_CT_TX_FIFO_S0 = 26, /**< SLINK control register(26) (r/-): log2(TX FIFO size) bit 0 */
|
SLINK_STATUS_RX6_AVAIL = 6, /**< SLINK status register(6) (r/-): RX link 6 data available */
|
SLINK_CT_TX_FIFO_S1 = 27, /**< SLINK control register(27) (r/-): log2(TX FIFO size) bit 1 */
|
SLINK_STATUS_RX7_AVAIL = 7, /**< SLINK status register(7) (r/-): RX link 7 data available */
|
SLINK_CT_TX_FIFO_S2 = 28, /**< SLINK control register(28) (r/-): log2(TX FIFO size) bit 2 */
|
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SLINK_CT_TX_FIFO_S3 = 29, /**< SLINK control register(29) (r/-): log2(TX FIFO size) bit 3 */
|
SLINK_STATUS_TX0_FREE = 8, /**< SLINK status register(8) (r/-): TX link 0 ready to send */
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SLINK_STATUS_TX1_FREE = 9, /**< SLINK status register(9) (r/-): TX link 1 ready to send */
|
SLINK_CT_EN = 31 /**< SLINK control register(31) (r/w): SLINK controller enable */
|
SLINK_STATUS_TX2_FREE = 10, /**< SLINK status register(10) (r/-): TX link 2 ready to send */
|
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SLINK_STATUS_TX3_FREE = 11, /**< SLINK status register(11) (r/-): TX link 3 ready to send */
|
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SLINK_STATUS_TX4_FREE = 12, /**< SLINK status register(12) (r/-): TX link 4 ready to send */
|
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SLINK_STATUS_TX5_FREE = 13, /**< SLINK status register(13) (r/-): TX link 5 ready to send */
|
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SLINK_STATUS_TX6_FREE = 14, /**< SLINK status register(14) (r/-): TX link 6 ready to send */
|
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SLINK_STATUS_TX7_FREE = 15, /**< SLINK status register(15) (r/-): TX link 7 ready to send */
|
|
|
|
SLINK_STATUS_RX0_HALF = 16, /**< SLINK status register(16) (r/-): RX link 0 FIFO fill level is >= half-full */
|
|
SLINK_STATUS_RX1_HALF = 17, /**< SLINK status register(17) (r/-): RX link 1 FIFO fill level is >= half-full */
|
|
SLINK_STATUS_RX2_HALF = 18, /**< SLINK status register(18) (r/-): RX link 2 FIFO fill level is >= half-full */
|
|
SLINK_STATUS_RX3_HALF = 19, /**< SLINK status register(19) (r/-): RX link 3 FIFO fill level is >= half-full */
|
|
SLINK_STATUS_RX4_HALF = 20, /**< SLINK status register(20) (r/-): RX link 4 FIFO fill level is >= half-full */
|
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SLINK_STATUS_RX5_HALF = 21, /**< SLINK status register(21) (r/-): RX link 5 FIFO fill level is >= half-full */
|
|
SLINK_STATUS_RX6_HALF = 22, /**< SLINK status register(22) (r/-): RX link 6 FIFO fill level is >= half-full */
|
|
SLINK_STATUS_RX7_HALF = 23, /**< SLINK status register(23) (r/-): RX link 7 FIFO fill level is >= half-full */
|
|
|
|
SLINK_STATUS_TX0_HALF = 24, /**< SLINK status register(24) (r/-): TX link 0 FIFO fill level is > half-full */
|
|
SLINK_STATUS_TX1_HALF = 25, /**< SLINK status register(25) (r/-): TX link 1 FIFO fill level is > half-full */
|
|
SLINK_STATUS_TX2_HALF = 26, /**< SLINK status register(26) (r/-): TX link 2 FIFO fill level is > half-full */
|
|
SLINK_STATUS_TX3_HALF = 27, /**< SLINK status register(27) (r/-): TX link 3 FIFO fill level is > half-full */
|
|
SLINK_STATUS_TX4_HALF = 28, /**< SLINK status register(28) (r/-): TX link 4 FIFO fill level is > half-full */
|
|
SLINK_STATUS_TX5_HALF = 29, /**< SLINK status register(29) (r/-): TX link 5 FIFO fill level is > half-full */
|
|
SLINK_STATUS_TX6_HALF = 30, /**< SLINK status register(30) (r/-): TX link 6 FIFO fill level is > half-full */
|
|
SLINK_STATUS_TX7_HALF = 31 /**< SLINK status register(31) (r/-): TX link 7 FIFO fill level is > half-full */
|
};
|
};
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
| Line 1038... |
Line 1070... |
|
|
/** NEOLED control register bits */
|
/** NEOLED control register bits */
|
enum NEORV32_NEOLED_CT_enum {
|
enum NEORV32_NEOLED_CT_enum {
|
NEOLED_CT_EN = 0, /**< NEOLED control register(0) (r/w): NEOLED global enable */
|
NEOLED_CT_EN = 0, /**< NEOLED control register(0) (r/w): NEOLED global enable */
|
NEOLED_CT_MODE = 1, /**< NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) */
|
NEOLED_CT_MODE = 1, /**< NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) */
|
NEOLED_CT_BSCON = 2, /**< NEOLED control register(2) (r/w): buffer status configuration -> busy_flag/IRQ config (0=at least one free entry, 1=whole buffer empty) */
|
NEOLED_CT_STROBE = 2, /**< NEOLED control register(2) (r/w): Strobe (0=send normal data, 1=send RESET command on data write) */
|
NEOLED_CT_PRSC0 = 3, /**< NEOLED control register(3) (r/w): Clock prescaler select bit 0 (pulse-clock speed select) */
|
NEOLED_CT_PRSC0 = 3, /**< NEOLED control register(3) (r/w): Clock prescaler select bit 0 (pulse-clock speed select) */
|
NEOLED_CT_PRSC1 = 4, /**< NEOLED control register(4) (r/w): Clock prescaler select bit 1 (pulse-clock speed select) */
|
NEOLED_CT_PRSC1 = 4, /**< NEOLED control register(4) (r/w): Clock prescaler select bit 1 (pulse-clock speed select) */
|
NEOLED_CT_PRSC2 = 5, /**< NEOLED control register(5) (r/w): Clock prescaler select bit 2 (pulse-clock speed select) */
|
NEOLED_CT_PRSC2 = 5, /**< NEOLED control register(5) (r/w): Clock prescaler select bit 2 (pulse-clock speed select) */
|
//
|
//
|
NEOLED_CT_BUFS_0 = 6, /**< NEOLED control register(6) (r/-): log2(tx buffer size) bit 0 */
|
NEOLED_CT_BUFS_0 = 6, /**< NEOLED control register(6) (r/-): log2(tx buffer size) bit 0 */
|
| Line 1066... |
Line 1098... |
NEOLED_CT_T_ONE_H_1 = 21, /**< NEOLED control register(21) (r/w): pulse-clock ticks per ONE high-time bit 1 */
|
NEOLED_CT_T_ONE_H_1 = 21, /**< NEOLED control register(21) (r/w): pulse-clock ticks per ONE high-time bit 1 */
|
NEOLED_CT_T_ONE_H_2 = 22, /**< NEOLED control register(22) (r/w): pulse-clock ticks per ONE high-time bit 2 */
|
NEOLED_CT_T_ONE_H_2 = 22, /**< NEOLED control register(22) (r/w): pulse-clock ticks per ONE high-time bit 2 */
|
NEOLED_CT_T_ONE_H_3 = 23, /**< NEOLED control register(23) (r/w): pulse-clock ticks per ONE high-time bit 3 */
|
NEOLED_CT_T_ONE_H_3 = 23, /**< NEOLED control register(23) (r/w): pulse-clock ticks per ONE high-time bit 3 */
|
NEOLED_CT_T_ONE_H_4 = 24, /**< NEOLED control register(24) (r/w): pulse-clock ticks per ONE high-time bit 4 */
|
NEOLED_CT_T_ONE_H_4 = 24, /**< NEOLED control register(24) (r/w): pulse-clock ticks per ONE high-time bit 4 */
|
//
|
//
|
NEOLED_CT_TX_STATUS = 30, /**< NEOLED control register(30) (r/-): serial transmit engine still busy when set */
|
NEOLED_CT_TX_EMPTY = 28, /**< NEOLED control register(28) (r/-): TX FIFO is empty */
|
NEOLED_CT_BUSY = 31 /**< NEOLED control register(31) (r/-): busy / buffer status flag (configured via #NEOLED_CT_BSCON) */
|
NEOLED_CT_TX_HALF = 29, /**< NEOLED control register(29) (r/-): TX FIFO is at least half-full */
|
|
NEOLED_CT_TX_FULL = 30, /**< NEOLED control register(30) (r/-): TX FIFO is full */
|
|
NEOLED_CT_TX_BUSY = 31 /**< NEOLED control register(31) (r/-): busy / buffer status flag (configured via #NEOLED_CT_BSCON) */
|
};
|
};
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
| Line 1107... |
Line 1141... |
enum NEORV32_SYSINFO_FEATURES_enum {
|
enum NEORV32_SYSINFO_FEATURES_enum {
|
SYSINFO_FEATURES_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
|
SYSINFO_FEATURES_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
|
SYSINFO_FEATURES_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
|
SYSINFO_FEATURES_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
|
SYSINFO_FEATURES_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
|
SYSINFO_FEATURES_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
|
SYSINFO_FEATURES_MEM_INT_DMEM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */
|
SYSINFO_FEATURES_MEM_INT_DMEM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */
|
SYSINFO_FEATURES_MEM_EXT_ENDIAN = 4, /**< SYSINFO_FEATURES (4) (r/-): External bus interface uses BIG-endian byte-order when 1 (via package.xbus_big_endian_c constant) */
|
SYSINFO_FEATURES_MEM_EXT_ENDIAN = 4, /**< SYSINFO_FEATURES (4) (r/-): External bus interface uses BIG-endian byte-order when 1 (via MEM_EXT_BIG_ENDIAN generic) */
|
SYSINFO_FEATURES_ICACHE = 5, /**< SYSINFO_FEATURES (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */
|
SYSINFO_FEATURES_ICACHE = 5, /**< SYSINFO_FEATURES (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */
|
|
|
SYSINFO_FEATURES_OCD = 14, /**< SYSINFO_FEATURES (14) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */
|
SYSINFO_FEATURES_OCD = 14, /**< SYSINFO_FEATURES (14) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */
|
SYSINFO_FEATURES_HW_RESET = 15, /**< SYSINFO_FEATURES (15) (r/-): Dedicated hardware reset of core registers implemented when 1 (via package's dedicated_reset_c constant) */
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SYSINFO_FEATURES_HW_RESET = 15, /**< SYSINFO_FEATURES (15) (r/-): Dedicated hardware reset of core registers implemented when 1 (via package's dedicated_reset_c constant) */
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